poster

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

Authors:

Yohei Nakata,

Shunsuke Okumura,

Hiroshi Kawaguchi,

Masahiko YoshimotoAuthors Info & Claims

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

Pages 219 - 224

https://doi.org/10.1145/1840845.1840888

Published: 18 August 2010 Publication History

Get Access

Abstract

This paper presents a novel cache architecture using 7T/14T hybrid SRAM, which can dynamically improve its reliability with control lines. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. The proposed scheme is suitable for dynamic voltage and frequency scaling (DVFS). In a 65-nm process, it can reduce the minimum operation voltage (V_min) to 0.5 V, which is 42% and 21% lower, respectively, than the conventional 6T SRAM and the cache word-disable scheme. The respective power reductions are 90% and 65%.

References

[1]

Itoh, K., "Low-voltage scaling limitations for nanoscale CMOS LSIs," International Conference on Ultimate Integration of Silicon (ULIS), pp. 3--6, Mar. 2008.

Crossref

Google Scholar

[2]

Wilkerson, C.; Gao, H.; Alameldeen, A.R.; Chishti, Z.; Khellah, M.; Lu, S.-L., "Trading off Cache Capacity for Reliability to Enable Low Voltage Operation," International Symposium on Computer Architecture (ISCA), pp. 203--214, Jun. 2008

Digital Library

Google Scholar

[3]

Ozdemir, S.; Sinha, D.; Memik, G.; Adams, J.; Zhou, H., "Yield-Aware Cache Architectures," Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 15--25, Dec. 2006.

Digital Library

Google Scholar

[4]

Agarwal, A.; Paul, B.C.; Mahmoodi, H.; Datta, A.; Roy, K., "A process-tolerant cache architecture for improved yield in nanoscale technologies," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 1, pp. 27--38, Jan. 2005.

Digital Library

Google Scholar

[5]

Fujiwara, H.; Okumura S.; Iguchi, Y.; Noguchi, H.; Kawaguchi, H.; and Yoshimoto, M., "A Dependable SRAM with 7T/14T Memory Cells," IEICE Transaction. on Electronics, vol. E92-C, no. 4, pp. 423--432, Apr. 2009.

Google Scholar

[6]

Kulkarni, J.P.; Kim, K.; Roy, K., "A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM," IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp. 2303--2313, Oct. 2007.

Crossref

Google Scholar

[7]

Stackhouse, B.; Bhimji, S.; Bostak, C.; Bradley, D.; Cherkauer, B.; Desai, J.; Francom, E.; Gowan, M.; Gronowski, P.; Krueger, D.; Morganti, C.; Troyer, S., "A 65 nm 2-Billion Transistor Quad-Core Itanium Processor," IEEE Journal of Solid-State Circuits, vol. 44, no.1, pp. 18--31, Jan. 2009.

Crossref

Google Scholar

[8]

Renau, J.; Fraguela, B.; Tuck, J.; Liu, W.; Prvulovic, M.; Ceze, L.; Strauss, K.; Sarangi, S.; Sack, P.; Montesinos, P., "SESC Simulator," Jan. 2005. http://sesc.sourceforge.net.

Google Scholar

[9]

Seevinck, E.; List, F.J.; Lohstroh, J., "Static-noise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, no.5, pp. 748--754, Oct. 1987.

Crossref

Google Scholar

[10]

Heald, R.; Wang, P., "Variability in sub-100 nm SRAM designs," IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 347--352, Nov. 2004.

Digital Library

Google Scholar

[11]

Yoshimoto, M.; Anami, K.; Shinohara, H.; Yoshihara, T.; Takagi,H.; Nagao, S.; Kayano, S.; Nakano, T., "A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM," IEEE Journal of Solid-State Circuits, vol. 18, no.5, pp.479--485, Oct. 1983.

Crossref

Google Scholar

Cited By

View all

Ling MLin QTan KShao TShen SYang J(2021)A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold VoltagesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.312065329:12(2197-2209)Online publication date: Dec-2021
https://doi.org/10.1109/TVLSI.2021.3120653
Wang PChien YTsai SLin XTanjung RLin YSyu SLin TWang JChen T(2017)ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric ArchitecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.264217025:12(3341-3354)Online publication date: Dec-2017
https://doi.org/10.1109/TVLSI.2016.2642170
Chen YTang YLiu YWu AHwang T(2017)A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability EnhancementsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.261499325:3(820-832)Online publication date: Mar-2017
https://doi.org/10.1109/TVLSI.2016.2614993
Show More Cited By

Index Terms

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory
      2. Static memory

Recommendations

Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
ISQED '08: Proceedings of the 9th international symposium on Quality Electronic Design

We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SRAM module is reduced from 550mV to 220mV. A novel error-tolerant ...
Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap
Abstract
The device scaling restricted due to the limitation of the subthreshold swing of the MOS transistor, which is not less than 60 mV/dec. The researchers are concentrating more on power efficient techniques for advanced, more featured, ...
An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body---source ...

Comments

Information & Contributors

Information

Published In

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

August 2010

458 pages

ISBN:9781450301466

DOI:10.1145/1840845

General Chairs:
Vojin Oklobdzija
University of Texas, Dallas
,
Barry Pangle
Mentor Graphics
,
Naehyuck Chang
Seoul National University
,
Program Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign
,
Chris H. Kim
University of Minnesota

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

IEEE CAS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 August 2010

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Poster

Conference

ISLPED'10

Sponsor:

SIGDA

ISLPED'10: International Symposium on Low Power Electronics and Design

August 18 - 20, 2010

Texas, Austin, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
137
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)1

Reflects downloads up to 30 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Ling MLin QTan KShao TShen SYang J(2021)A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold VoltagesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.312065329:12(2197-2209)Online publication date: Dec-2021
https://doi.org/10.1109/TVLSI.2021.3120653
Wang PChien YTsai SLin XTanjung RLin YSyu SLin TWang JChen T(2017)ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric ArchitecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.264217025:12(3341-3354)Online publication date: Dec-2017
https://doi.org/10.1109/TVLSI.2016.2642170
Chen YTang YLiu YWu AHwang T(2017)A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability EnhancementsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.261499325:3(820-832)Online publication date: Mar-2017
https://doi.org/10.1109/TVLSI.2016.2614993
Chen YTang YLiu YWu AHwang TFanucci LTeich J(2016)A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancementsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971826(79-84)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971826
Nakata YOkumura SKawaguchi HYoshimoto M(2012)0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing SchemeIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.5.325(32-43)Online publication date: 2012
https://doi.org/10.2197/ipsjtsldm.5.32
YOSHIMOTO SAMASHITA TOKUMURA SNII KYOSHIMOTO MKAWAGUCHI H(2012)Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI ProcessIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.1359E95.A:8(1359-1365)Online publication date: 2012
https://doi.org/10.1587/transfun.E95.A.1359
Noguchi HOkumura STakagi TKugata KYoshimoto MKawaguchi H(2011)0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770728(1-4)Online publication date: Mar-2011
https://doi.org/10.1109/ISQED.2011.5770728
Yoshimoto SAmashita TOkumura SYamaguchi KYoshimoto MKawaguchi H(2011)Bit error and soft error hardenable 7T/14T SRAM with 150-nm FD-SOI process2011 International Reliability Physics Symposium10.1109/IRPS.2011.5784596(SE.3.1-SE.3.6)Online publication date: Apr-2011
https://doi.org/10.1109/IRPS.2011.5784596

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation

Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques