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NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime

Published: 18 August 2010 Publication History

Abstract

Scaling process technology necessitates the introduction of wide design-time guard bands that ensure lifetime reliability as circuits wear out over time. In this paper, we show how to utilize this knowledge of the guard band and a predictive model to absolutely improve processor power consumption and lifetime without impacting the processor performance against Negative Bias Temperature Instability (NBTI) degradation. For the first time, we evaluate the long-term potential and impact of NBTI-aware job-to-core mapping quantitatively and account for process variations in the system. Our approach saves up to 16% of the dynamic energy consumed and improve lifetime by two years.

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Cited By

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  • (2024)Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332316343:5(1580-1593)Online publication date: May-2024
  • (2023)Power-Efficient and Aging-Aware Primary/Backup Technique for Heterogeneous Embedded SystemsIEEE Transactions on Sustainable Computing10.1109/TSUSC.2023.32821648:4(715-726)Online publication date: Oct-2023
  • (2022)Run-Time Thermal Management for Lifetime Optimization in Low-Power DesignsElectronics10.3390/electronics1103041111:3(411)Online publication date: 29-Jan-2022
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    cover image ACM Conferences
    ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
    August 2010
    458 pages
    ISBN:9781450301466
    DOI:10.1145/1840845
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 18 August 2010

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    Author Tags

    1. DVFS
    2. NBTI
    3. energy efficiency
    4. process variation
    5. wearout

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    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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    View all
    • (2024)Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332316343:5(1580-1593)Online publication date: May-2024
    • (2023)Power-Efficient and Aging-Aware Primary/Backup Technique for Heterogeneous Embedded SystemsIEEE Transactions on Sustainable Computing10.1109/TSUSC.2023.32821648:4(715-726)Online publication date: Oct-2023
    • (2022)Run-Time Thermal Management for Lifetime Optimization in Low-Power DesignsElectronics10.3390/electronics1103041111:3(411)Online publication date: 29-Jan-2022
    • (2021)Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore ProcessorsIEEE Transactions on Computers10.1109/TC.2020.300657170:7(1106-1119)Online publication date: 1-Jul-2021
    • (2019)Modeling and Evaluating the Gate Length Dependence of BTIIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2018.288585066:9(1527-1531)Online publication date: Sep-2019
    • (2019)ROAD: Improving Reliability of Multi-core System via Asymmetric Aging2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD45719.2019.8942178(1-8)Online publication date: Nov-2019
    • (2018)Exploiting Aging Benefits for the Design of Reliable Drowsy Cache MemoriesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.272939937:7(1345-1357)Online publication date: Jul-2018
    • (2018)Recent advances in in-situ and in-field aging monitoring and compensation for integrated circuits: Invited paper2018 IEEE International Reliability Physics Symposium (IRPS)10.1109/IRPS.2018.8353612(5C.1-1-5C.1-6)Online publication date: Mar-2018
    • (2018)Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimationIET Computers & Digital Techniques10.1049/iet-cdt.2018.508112:6(268-278)Online publication date: 3-Oct-2018
    • (2017)SSAGAACM Transactions on Design Automation of Electronic Systems10.1145/301416322:3(1-20)Online publication date: 21-Apr-2017
    • Show More Cited By

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