Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
research-article

Implementation of a programming environment with a multithread model for reconfigurable systems

Published: 14 January 2011 Publication History

Abstract

Reconfigurable systems are known to be able to achieve higher performance than traditional microprocessor architecture for many application fields. However, in order to extract a full potential of the reconfigurable systems, programmers often have to design and describe the best suited code for their target architecture with specialized knowledge. The aim of this paper is to assist the users of reconfigurable systems by implementing a translator with a multithread model. The experimental results show our translator automatically generates efficient performance-aware code segments including DMA transfer and shift registers for memory access optimization.

References

[1]
COINS Compiler Infrastructre. http://coins-project.is.titech.ac.jp/international/index.html/.
[2]
CUDA. http://www.nvidia.com/object/cuda_home.html.
[3]
OpenCL. http://www.khronos.org/opencl/.
[4]
OpenMP. http://openmp.org/wp/.
[5]
J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang. Platform-based behavior-level and system-level synthesis. Proceedings of the IEEE International SOC Conference, pages 199--202, 2006.
[6]
M. Gokhale and J. Stone. NAPA C: Compiling for a hybrid RISC/FPGA architecture. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'98, pages 126--134, 1998.
[7]
J. Hauser and J. Wawrzynek. Garp: a mips processor with a reconfigurable coprocessor. Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, 0:12, 1997.
[8]
O. Mencer. Computing with FPGAs. In Proceedings of the 10th International Symposium on Low-Power and High-Speed Chips (COOL Chips X), pages 327--343, 2006.
[9]
M. Miyata, H. Tsuchiya, Y. Shibata, and K. Oguri. An implementation technique of multi-cycled arithmetic functions for a dynamically reconfigurable processor. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'06), pages 689--692, 2006.
[10]
M. Motomura. A dynamically reconfigurable processor architecture. Microprocessor Forum, Oct. 2002.
[11]
B. Nelson. Fpga design productivity--a discussion of the state of the art and a research agenda. Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC'09), page 1, Mar. 2009.
[12]
D. S. Poznanovic. Application development on the SRC Computers, inc. systems. Parallel and Distributed Processing Symposium, 1:78a, 2005.
[13]
A. Putnam, D. Bennett, E. Dellinger, J. Mason, P. Sundararajan, and S. Eggers. Chimps: A c-level compilation flow for hybrid cpu-fpga architectures. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'08), pages 173--178, 2008.
[14]
S. Shida, Y. Shibata, K. Oguri, and D. A. Buell. Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'07), pages 589--592, Aug. 2007.

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News  Volume 38, Issue 4
September 2010
96 pages
ISSN:0163-5964
DOI:10.1145/1926367
Issue’s Table of Contents

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 14 January 2011
Published in SIGARCH Volume 38, Issue 4

Check for updates

Qualifiers

  • Research-article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • 0
    Total Citations
  • 140
    Total Downloads
  • Downloads (Last 12 months)1
  • Downloads (Last 6 weeks)0
Reflects downloads up to 30 Aug 2024

Other Metrics

Citations

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media