research-article

A hybrid hardware--software technique to improve reliability in embedded processors

Authors:

Roshan G. Ragel and

Sri ParameswaranAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 10, Issue 3

Article No.: 36, Pages 1 - 16

https://doi.org/10.1145/1952522.1952529

Published: 05 May 2011 Publication History

Abstract

Numerous methods have been described in research literature with methods to improve reliability of processors by the use of control-flow checking. High performance and code-size penalties cripple the proposed software approaches, while hardware approaches are not scalable and are thus rarely implemented in real embedded systems. In this article, we show that by including control-flow checking as an issue to be considered when designing as embedded processor, we are able to reduce overheads considerably and still provide a scalable solution to this problem. The technique described in this article includes architectural improvements to the processor and binary rewriting of the application. Architectural refinement incorporates additional instructions to the instruction set architecture, while the binary rewriting utilizes these additional instructions into the program flow. Applications from an embedded systems benchmark suite have been used to test and evaluate the system. Our approach increased code size by only 5.55% to 13.5% and reduced performance by just 0.54% to 2.83% for eight different industry standard benchmarks. The additional hardware overhead due to the additional instruction in the design is just 2.70%. In contrast, the state-of-the-art software-only approach required 50% to 150% additional code, and reduced performance by 53.5% to 99.5% when monitoring was inserted. Fault injection analysis demonstrates that our solution is capable of capturing and recovering from all the injected control-flow errors, while the software-only approach detected 87% of the injected control-flow errors.

References

[1]

Alkhalifa, Z., Nair, V., Krishnamurthy, N., and Abraham, J. 1999. Design and evaluation of system-level checks for on-line control flow error detection. IEEE Trans. Parall. Distrib. Syst. 10, 6, 627--641.

Digital Library

[2]

Bagchi, S., Liu, Y., Whisnant, K., Kalbarczyk, Z., Iyer, R. K., Levendel, Y., and Votta, L. 2001. A framework for database audit and control flow checking for a wireless telephone network controller. In Proceedings of the International Conference on Dependable Systems and Networks. IEEE, Los Alamitos, CA, 225--234.

Digital Library

[3]

Burger, D. and Austin, T. M. 1997. The simple scalar tool set, version 2.0. SIGARCH Comput. Archit. News 25, 3, 13--25.

Digital Library

[4]

Delord, X. and Saucier, G. 1990. Control flow checking in pipelined RISC microprocessors: The Motorola MC88100 case study. In Proceedings of the Euro-Micro Workshop on Real-Time. IEEE, Los Alamitos, CA, 162--169.

[5]

Delord, X. and Saucier, G. 1991. Formalizing signature analysis for control flow checking of pipelined RISC microprocessors. In Proceedings of International Test Conference. IEEE, Los Alamitos, CA, 936--945.

Digital Library

[6]

Eschermann, B. 1992. On combining offline BIST and online control flow checking. In Proceedings of the 22nd International Symposium on Fault-Tolerant Computing. IEEE, Los Alamitos, CA, 298--305.

[7]

Fisher, J. A. 1999. Customized instruction-sets for embedded processors. In Proceedings of the 36th Conference on Design Automation. ACM, New York, 253--257.

Digital Library

[8]

Gaisler, J. 1994. Concurrent error-detection and modular fault-tolerance in a 32-bit processing core for embedded space flight applications. In Proceedings of the 24th Annual International Symposium on Fault-Tolerant Computing. IEEE, Los Alamitos, CA, 128--130.

[9]

Goloubeva, O., Rebaudengo, M., Reorda, M., and Violante, M. 2005. Improved software-based processor control-flow errors detection technique. In Proceedings of the Annual Reliability and Maintainability Symposium. IEEE, Los Alamitos, CA, 583--589.

[10]

Goloubeva, O., Rebaudengo, M. S., Reorda, M. S., and Violante, M. 2003. Soft-error detection using control flow assertions. In Proceedings of the 18th International Symposium on Defect and Fault-Tolerance in VLSI Systems. IEEE, Los Alamitos, CA, 581--588.

Digital Library

[11]

Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., and Brown, R. B. 2001. Mibench: A free, commercially representative embedded benchmark suite. In Proceedings of 4th Annual Workshop on Workload Characterization. IEEE, Los Alamitos, CA, 83--94.

Digital Library

[12]

Kanawati, G., Nair, V., Krishnamurthy, N., and Abraham, J. 1996. Evaluation of integrated system-level checks for on-line error detection. In Proceedings of International Computer Performance and Dependability Symposium. IEEE, Los Alamitos, CA, 292--301.

Digital Library

[13]

Leveugle, R., Michel, T., and Saucier, G. 1990. Design of microprocessors with built-in online test. In Proceedings of the 20th International Symposium on Fault-Tolerant Computing. IEEE, Los Alamitos, CA, 450--456.

[14]

Lu, D. J. 1982. Watchdog processors and structural integrity checking. IEEE Trans. Comput. 31, 7, 681--685.

Digital Library

[15]

Lyu, M. R. 1995. Software Fault-Tolerance. John Wiley and Sons Ltd, Hoboken, NJ.

Digital Library

[16]

Madeira, H. and Silva, J. 1991. Online signature learning and checking: Experimental evaluation. In Proceedings of 5th Annual European Computer Conference on Advanced Computer Technology, Reliable Systems and Applications. IEEE, Los Alamitos, CA, 642--643.

[17]

Mahmood, A. and McCluskey, E. J. 1988. Concurrent error detection using watchdog processors: A survey. IEEE Trans. Comput. 37, 2, 160--174.

Digital Library

[18]

McFearin L. and Nair V.S.S. 1995. Control-flow checking using assertions. In Proceedings of the 5th International Working Conference on Dependable Computing for Critical Applications. IEEE, Los Alamitos, CA, 103--112.

[19]

Michel, T., Leveugle, R., Gaume, F., and Roane, R. 1992. An application specific microprocessor with two-level built-in control flow checking capabilities. In Proceedings of the European Conference on Application Specific Integrated Circuits. IEEE, Los Alamitos, CA, 310--313.

[20]

Michel, T., Leveugle, R., and Saucier, G. 1991. A new approach to control flow checking without program modification. In Proceedings of the 21st International Symposium on Fault-Tolerant Computing. IEEE, Los Alamitos, CA, 334--341.

[21]

Milenkovic, M. 2005. Architectures for run-time verification of code integrity. Ph.D. thesis, The University of Alabama in Huntsville, Huntsville, AL.

Digital Library

[22]

Miremadi, G., Harlsson, J., Gunneflo, U., and Torin, J. 1992. Two software techniques for online error detection. In Proceedings of the 22nd International Symposium on Fault-Tolerant Computing. IEEE, Los Alamitos, CA, 328--335.

[23]

Miremadi, G., Ohlsson, J., Rimn, M., and Karlsson, J. 1995. Use of time and address signatures for control flow checking. In Proceedings of the 5th International Working Conference on Dependable Computing for Critical Applications. IEEE, Los Alamitos, CA, 201--221.

[24]

Nair V. S. S., Kim H., Krishnamurthy N., and Abraham J. A. 1996. Design and evaluation of automated high-level checks for signal processing applications. In Proceedings of the Advanced Algorithms and Architectures for Signal Processing Conference. IEEE, Los Alamitos, CA, 292--301.

[25]

Namjoo, M. 1982. Techniques for concurrent testing of VLSI processor operation. In Proceedings of the International Test Conference. IEEE, Los Alamitos, CA, 461--468.

[26]

Noubir, G. and Choueiry, B. 1996. Algebraic techniques for the optimization of control flow checking. In Proceedings of the Annual Symposium on Fault-Tolerant Computing. IEEE, Los Alamitos, CA, 128--137.

Digital Library

[27]

Ohlsson, J. and Rimen, M. 1995. Implicit signature checking. In Proceedings of the 25th International Symposium on Fault-Tolerant Computing. IEEE, Los Alamitos, CA, 218--227.

Digital Library

[28]

Ohlsson, J., Rimen, M., and Gunneflo, U. 1992. A study of the effects of transient fault injection into a 32-bit RISC with built-in watchdog. In Proceedings of the 22nd International Symposium on Fault-Tolerant Computing. IEEE, Los Alamitos, CA, 316--325.

[29]

Peddersen, J., Shee, S. L., Janapsatya, A., and Parameswaran, S. 2005. Rapid embedded hardware/software system generation. In Proceedings of the 18th International Conference on Design Held Jointly with the 4th International Conference on Embedded Systems Design. IEEE, Los Alamitos, CA, 111--116.

Digital Library

[30]

Ramamurthy, B. and Upadhyaya, S. 1995. Watchdog processor-assisted fast recovery in distributed systems. In Proceedings of the 5th International Working Conference on Dependable Computing for Critical Applications. IEEE, Los Alamitos, CA, 125--134.

[31]

Rao, T. 1974. Error Coding for Arithmetic Processors. Academic Press, Orlando, FL.

Digital Library

[32]

Saxena, N. and McCluskey, E. 1990. Control-flow checking using watchdog assists and extended-precision checksums. IEEE Trans. Comput. 39, 4, 554--558.

Digital Library

[33]

Schuette, M. A. and Shen, J. P. 1987. Processor control flow monitoring using signature instruction streams. IEEE Trans. Comput. 36, 3, 264--276.

Digital Library

[34]

Schuette, M. A., Shen, J. P., Siewiorek, D. P., and Zhu, Y. X. 1986. Experimental evaluation of two concurrent error detection schemes. In Digestions of Papers of the 16th Annual International Symposium of Fault-Tolerant Computing. IEEE, Los Alamitos, CA, 138--143.

[35]

Sosnowski, J. 1988. Detection of control-flow errors using signature and checking instructions. In Proceedings of the International Test Conference. IEEE, Los Alamitos, CA, 81--88.

Digital Library

[36]

Sutter, B. D., Bus, B. D., and Bosschere, K. D. 2005. Link-time binary rewriting techniques for program compaction. ACM Trans. Program. Lang. Syst. 27, 5, 882--945.

Digital Library

[37]

The PEAS Team. 2002. ASIP Meister, Available at http://www.eda-meister.org/asip-meister/.

[38]

Upadhyaya, S. and Ramamurthy, B. 1994. Concurrent process monitoring with no reference signatures. IEEE Trans. Comput. 43, 475--480.

Digital Library

[39]

Wilken, K. and Shen, J. 1990. Continuous signature monitoring: Low-cost concurrent detection of processor control errors. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 9, 6, 629--641.

Digital Library

[40]

Yau, S. S. and Chen, F.-C. 1980. An approach to concurrent control flow checking. IEEE Trans. Softw. Engin. 6, 2, 126--137.

Digital Library

Cited By

Trochun YWang ZRokovyi OPeng GAlienin OLai GGordienko YStirenko S(2021)Hurricane Damage Detection by Classic and Hybrid Classic-Quantum Neural Networks2021 International Conference on Space-Air-Ground Computing (SAGC)10.1109/SAGC52752.2021.00033(152-156)Online publication date: Oct-2021
https://doi.org/10.1109/SAGC52752.2021.00033
Trochun YStirenko SRokovyi OAlienin OPavlov EGordienko Y(2021)Hybrid Classic-Quantum Neural Networks for Image Classification2021 11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)10.1109/IDAACS53288.2021.9661011(968-972)Online publication date: 22-Sep-2021
https://dl.acm.org/doi/10.1109/IDAACS53288.2021.9661011
Trochun YPavlov EStirenko SGordienko Y(2021)Impact of Hybrid Neural Network Structure on Performance of Multiclass ClassificationIEEE EUROCON 2021 - 19th International Conference on Smart Technologies10.1109/EUROCON52738.2021.9535586(152-156)Online publication date: 6-Jul-2021
https://doi.org/10.1109/EUROCON52738.2021.9535586
Show More Cited By

Index Terms

A hybrid hardware--software technique to improve reliability in embedded processors
1. Hardware
  1. Hardware test
  2. Robustness

Recommendations

A retargetable register allocation framework for embedded processors
LCTES '04

This paper describes the FlexCC2 register allocation framework. FlexCC2 is an optimizing retargetable C compiler for embedded processors, and in particular for DSP processors. Embedded processors often contain features such as irregular and constrained ...
Read More
A retargetable register allocation framework for embedded processors
LCTES '04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

This paper describes the FlexCC2 register allocation framework. FlexCC2 is an optimizing retargetable C compiler for embedded processors, and in particular for DSP processors. Embedded processors often contain features such as irregular and constrained ...
Read More
Branchless cycle prediction for embedded processors
SAC '06: Proceedings of the 2006 ACM symposium on Applied computing

Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branch instruction among those fetched.In this work we introduce Branchless ...
Read More

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 10, Issue 3

April 2011

205 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/1952522

Issue’s Table of Contents

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 05 May 2011

Accepted: 01 May 2010

Revised: 01 September 2008

Received: 01 May 2007

Published in TECS Volume 10, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

19
Total Citations
View Citations
639
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)1

Other Metrics

View Author Metrics

Citations

Cited By

Trochun YWang ZRokovyi OPeng GAlienin OLai GGordienko YStirenko S(2021)Hurricane Damage Detection by Classic and Hybrid Classic-Quantum Neural Networks2021 International Conference on Space-Air-Ground Computing (SAGC)10.1109/SAGC52752.2021.00033(152-156)Online publication date: Oct-2021
https://doi.org/10.1109/SAGC52752.2021.00033
Trochun YStirenko SRokovyi OAlienin OPavlov EGordienko Y(2021)Hybrid Classic-Quantum Neural Networks for Image Classification2021 11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)10.1109/IDAACS53288.2021.9661011(968-972)Online publication date: 22-Sep-2021
https://dl.acm.org/doi/10.1109/IDAACS53288.2021.9661011
Trochun YPavlov EStirenko SGordienko Y(2021)Impact of Hybrid Neural Network Structure on Performance of Multiclass ClassificationIEEE EUROCON 2021 - 19th International Conference on Smart Technologies10.1109/EUROCON52738.2021.9535586(152-156)Online publication date: 6-Jul-2021
https://doi.org/10.1109/EUROCON52738.2021.9535586
Gopalakrishnan SSingh V(2019)Soft-error reliable architecture for future microprocessorsIET Computers & Digital Techniques10.1049/iet-cdt.2018.5015Online publication date: 28-Jan-2019
https://doi.org/10.1049/iet-cdt.2018.5015
Aponte-Moreno AMoncada ARestrepo-Calle FPedraza C(2018)A review of approximate computing techniques towards fault mitigation in HW/SW systems2018 IEEE 19th Latin-American Test Symposium (LATS)10.1109/LATW.2018.8347241(1-6)Online publication date: Mar-2018
https://doi.org/10.1109/LATW.2018.8347241
Restrepo-Calle FMartínez-Álvarez ACuenca-Asensi SJimeno-Morenilla A(2018)Selective SWIFT-RJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5416-629:6(825-838)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1007/s10836-013-5416-6
Ahmad HSedaghat YRezaei M(2017)A performance counter-based control flow checking technique for multi-core processors2017 7th International Conference on Computer and Knowledge Engineering (ICCKE)10.1109/ICCKE.2017.8167922(461-465)Online publication date: Oct-2017
https://doi.org/10.1109/ICCKE.2017.8167922
Gopalakrishnan SSingh V(2017)REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2017.8244454(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/DFT.2017.8244454
Restrepo-Calle FCuenca-Asensi SMartínez-Álvarez A(2016)Reducing Implicit Overheads of Soft Error Mitigation Techniques Using Selective HardeningFPGAs and Parallel Architectures for Aerospace Applications10.1007/978-3-319-14352-1_17(259-278)Online publication date: 2016
https://doi.org/10.1007/978-3-319-14352-1_17
Rouf MSoontae Kim (2015)Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor PipelineIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.229757323:1(131-141)Online publication date: Jan-2015
https://doi.org/10.1109/TVLSI.2013.2297573
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents