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Automated multi-cycle symbolic timing verification of microprocessor-based designs

Authors: Anurag P. Gupta, Daniel P. SiewiorekAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 113 - 119

https://doi.org/10.1145/196244.196299

Published: 06 June 1994 Publication History

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Cited By

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Zhang GLi BHuang XYin XZhuo CHashimoto MSchlichtmann U(2022)VirtualSync+: Timing Optimization With Virtual SynchronizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.315343341:12(5526-5540)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3153433
Jeong KKahng AKang S(2010)Toward effective utilization of timing exceptions in design optimization2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450401(54-61)Online publication date: Mar-2010
https://doi.org/10.1109/ISQED.2010.5450401
D'Silva VKroening DBenini LDe Micheli GAl-Hashimi BMueller W(2009)Fixed points for multi-cycle path detectionProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1875027(1710-1715)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1875027
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Index Terms

Automated multi-cycle symbolic timing verification of microprocessor-based designs
1. Hardware
  1. Hardware validation
    1. Functional verification
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits
      2. Sequential circuits

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Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 1994

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DAC94

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EDAC
SIGDA
IEEE-CAS

DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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June 22 - 26, 2025

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Cited By

View all

Zhang GLi BHuang XYin XZhuo CHashimoto MSchlichtmann U(2022)VirtualSync+: Timing Optimization With Virtual SynchronizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.315343341:12(5526-5540)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3153433
Jeong KKahng AKang S(2010)Toward effective utilization of timing exceptions in design optimization2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450401(54-61)Online publication date: Mar-2010
https://doi.org/10.1109/ISQED.2010.5450401
D'Silva VKroening DBenini LDe Micheli GAl-Hashimi BMueller W(2009)Fixed points for multi-cycle path detectionProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1875027(1710-1715)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1875027
D'Silva VKroening D(2009)Fixed points for multi-cycle path detection2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090938(1710-1715)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090938
Cheng LChen DWong MHutton MGovig JGielen G(2007)Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domainsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326149(370-375)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326149
Lei Cheng Deming Chen Wong MHutton MGovig J(2007)Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains2007 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2007.4397292(370-375)Online publication date: Nov-2007
https://doi.org/10.1109/ICCAD.2007.4397292
Yang KCheng KHirose F(2006)Efficient identification of multi-cycle false pathProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118390(360-365)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118390
Kai Yang Kwang-Ting Cheng (2006)Efficient identification of multi-cycle false pathAsia and South Pacific Conference on Design Automation, 2006.10.1109/ASPDAC.2006.1594709(360-365)Online publication date: 2006
https://doi.org/10.1109/ASPDAC.2006.1594709
Daga ABirmingham W(2006)Interface finite-state machinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.63121216:5(497-505)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.631212
Higuchi HMatsunaga YImai M(2004)Enhancing the performance of multi-cycle path analysis in an industrial settingProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015136(192-197)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015136
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