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Sequencer-based data path synthesis of regular iterative algorithms

Authors:

Mohammed Aloqeely,

C. Y. Roger ChenAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 155 - 160

https://doi.org/10.1145/196244.196317

Published: 06 June 1994 Publication History

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References

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Cited By

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Cong JFan YJiang WHassoun S(2006)Platform-based resource binding using a distributed register-file microarchitectureProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233648(709-715)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233648
Cong JFan YJiang W(2006)Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture2006 IEEE/ACM International Conference on Computer Aided Design10.1109/ICCAD.2006.320017(709-715)Online publication date: Nov-2006
https://doi.org/10.1109/ICCAD.2006.320017
Kwai DParhami B(2001)Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector QuantizationJournal of VLSI Signal Processing Systems10.5555/509243.281323228:3(235-243)Online publication date: 1-Jul-2001
https://dl.acm.org/doi/10.5555/509243.2813232
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Index Terms

Sequencer-based data path synthesis of regular iterative algorithms
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory

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DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 06 June 1994

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DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cong JFan YJiang WHassoun S(2006)Platform-based resource binding using a distributed register-file microarchitectureProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233648(709-715)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233648
Cong JFan YJiang W(2006)Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture2006 IEEE/ACM International Conference on Computer Aided Design10.1109/ICCAD.2006.320017(709-715)Online publication date: Nov-2006
https://doi.org/10.1109/ICCAD.2006.320017
Kwai DParhami B(2001)Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector QuantizationJournal of VLSI Signal Processing Systems10.5555/509243.281323228:3(235-243)Online publication date: 1-Jul-2001
https://dl.acm.org/doi/10.5555/509243.2813232
Balakrishnan MKhanna H(2000)Allocation of FIFO structures in RTL data pathsACM Transactions on Design Automation of Electronic Systems10.1145/348019.3480445:3(294-310)Online publication date: 1-Jul-2000
https://dl.acm.org/doi/10.1145/348019.348044
Srivatsan KChakrabarti CLucke L(1999)A new register allocation scheme for low-power data format convertersIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing10.1109/82.79371746:9(1250-1253)Online publication date: Jan-1999
https://doi.org/10.1109/82.793717
Dalkilic MPitchumani V(1999)Multi-schedule design space explorationIntegration, the VLSI Journal10.1016/S0167-9260(99)00007-327:2(87-112)Online publication date: 1-Jul-1999
https://dl.acm.org/doi/10.1016/S0167-9260%2899%2900007-3
Aloqeely M(1998)A simple alternative for storage allocation in high-level synthesisISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)10.1109/ISCAS.1998.705289(377-380)Online publication date: 1998
https://doi.org/10.1109/ISCAS.1998.705289
Khanna HBalakrishnan M(1997)Allocation of FIFO Structures in RTL Data PathsProceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications10.5555/523974.834922Online publication date: 4-Jan-1997
https://dl.acm.org/doi/10.5555/523974.834922
Khanna HBalakrishnan M(1997)Allocation of FIFO structures in RTL data pathsProceedings Tenth International Conference on VLSI Design10.1109/ICVD.1997.568064(130-133)Online publication date: 1997
https://doi.org/10.1109/ICVD.1997.568064
Kwai DParhami B(1996)FFT computation with linear processor arrays using a data-driven control schemeJournal of VLSI Signal Processing Systems10.5555/241369.281293513:1(57-66)Online publication date: 1-Aug-1996
https://dl.acm.org/doi/10.5555/241369.2812935
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Polylogarithmic Time Algorithms for Shortest Path Forests in Programmable Matter

A Data-Driven Path Synthesis Framework for Racing Games

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Polylogarithmic Time Algorithms for Shortest Path Forests in Programmable Matter

A Data-Driven Path Synthesis Framework for Racing Games

Control data path tradeoffs in high-level synthesis

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