research-article

A programmable and scalable technique to design spintronic logic circuits based on magnetic tunnel junctions

Authors:

David J. LiljaAuthors Info & Claims

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

Pages 7 - 12

https://doi.org/10.1145/1973009.1973012

Published: 02 May 2011 Publication History

Abstract

Exciting developments are taking place in the field of spintronics, particularly with the advances in the fabrication and characterization of devices such as Magnetic Tunnel Junctions (MTJ). The distinction of spintronic devices from conventional electronic devices makes it challenging to design efficient, scalable and low power logic circuits with MTJs. We propose a programmable and scalable technique to design MTJ-based logic circuits that are capable of implementing any 2-input logic truth table. We present the energy-delay trade-offs of this design with respect to circuit parameters. We also demonstrate that this circuit can be scaled to a 6-input logic function without incurring an increase in the energy consumption.

References

[1]

L. Berger. Emission of spin waves by a magnetic multilayer traversed by a current. Physical Review B, 54(13):9353--9358, 1996.

[2]

W. Gallagher and S. Parkin. Development of the magnetic tunnel junction mram at ibm: from first junctions to a 16-mb mram demonstrator chip. IBM Journal of Research and Development, 50(1):5--23, 2006.

Digital Library

[3]

J. Harms, F. Ebrahimi, X. Yao, and J.-P. Wang. Spice macromodel of spin-torque-transfer operated magnetic tunnel junctions. IEEE Transactions on Electronic Devices, 57(6):1425--1430, 2010.

[4]

M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto, H. Nagao, and H. Kano. A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram. IEEE International Electron Devices Meeting, IEDM Technical Digest, pages 459--462, 2005.

[5]

S. Lee, N. Kim, H. Yang, G. Lee, S. Lee, and H. Shin. The 3-bit gray counter based on magnetic-tunnel-junction elements. IEEE Transactions on Magnetics, 43(6):2677--2679, 2007.

[6]

A. Lyle, J. Harms, S. Patil, X. Yao, D. Lilja, and J.-P. Wang. Direct communication between magnetic tunnel junctions for non-volatile logic fan-out architecture. Applied Physics Letters, 97(15):152504--152506, 2010.

[7]

S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, H. Hasegawa, T. Endoh, H. Ohno, and T. Hanyu. Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions. Applied Physics Express, 1:091301--3, 2008.

[8]

H. Meng, J. Wang, and J.-P. Wang. A spintronics full adder for magnetic cpu. IEEE Electron Device Letters, 26(6):360--362, 2005.

[9]

J. S. Moodera, L. R. Kinder, T. M. Wong, and R. Meservey. Large magnetoresistance at room temperature in ferromagnetic thin film tunnel junctions. Physical Review Letters, 74(16):3273--3276, 1995.

[10]

E. B. Myers, D. C. Ralph, J. A. Katine, R. N. Louie, and R. A. Buhrman. Current-induced switching of domains in magnetic multilayer devices. Science, 285(5429):867--870, 1999.

[11]

S. Patil, A. Lyle, J. Harms, D. Lilja, and J.-P. Wang. Spintronic logic gates for spintronic data using magnetic tunnel junctions. IEEE International Conference on Computer Design (ICCD 2010), pages 125--131, 2010.

[12]

S. Patil, X. Yao, H. Meng, J.-P. Wang, and D. Lilja. Design of a spintronic arithmetic and logic unit using magnetic tunnel junctions. Proceedings of the 5th conference on Computing frontiers, pages 171--178, 2008.

Digital Library

[13]

J. Slonczewski. Current-driven excitation of magnetic multilayers. Journal of Magnetism and Magnetic Materials, 159(1-2):L1-L7, 1996.

[14]

S. Tehrani, J.M. Slaughter, E. Chen, M. Durlam, J. Shi, and M. DeHerrera. Progress and outlook for mram technology. IEEE Transactions on Magnetics, 35(5):2814--2819, 1999.

[15]

J. Wang, H. Meng, and J.-P. Wang. Programmable spintronics logic device based on a magnetic tunnel junction element. Journal of Applied Physics, 97(10):10D509, 2005.

[16]

J-P. Wang and X. Yao. Programmable spintronic logic devices for reconfigurable computation and beyond - history and outlook. Journal of Nanoelectronics and Optoelectronics, 3:12--23, 2008.

[17]

H. Zhao, A. Lyle, Y. Zhang, P. K. Amiri, G. Rowlands, Z. M. Zeng, J. Katine, H. W. Jiang, K. Galatsis, K. L. Wang, I. N. Krivorotov, and J.-P. Wang. Low writing energy and sub nano-second spin torque transfer switching of in-plane magnetic tunnel junction for stt-ram. To be published in Journal of Applied Physics, 2011.

[18]

W. Zhao, E. Belhaire, and C. Chappert. Spin-mtj based non-volatile flip-flop. 7th IEEE Conference on Nanotechnology (IEEE-NANO 2007), pages 399--402, 2007.

[19]

W. Zhao, E. Belhaire, C. Chappert, and P. Mazoyer. Spintronic device based non-volatile low standby power sram. IEEE Computer Society Annual Symposium on VLSI, pages 40--45, 2008.

Digital Library

[20]

W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, and B. Dieny. A non-volatile flip-flop in magnetic fpga chip. International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS), pages 323--326, 2006.

Cited By

Suzuki DNatsui MHanyu T(2012)Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2012.6292025(334-337)Online publication date: Aug-2012
https://doi.org/10.1109/MWSCAS.2012.6292025

Index Terms

A programmable and scalable technique to design spintronic logic circuits based on magnetic tunnel junctions
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits
    2. Semiconductor memory

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cover image ACM Conferences

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

May 2011

496 pages

ISBN:9781450306676

DOI:10.1145/1973009

General Chairs:
David Atienza
EPFL, Switzerland
,
Yuan Xie
Penn State University, USA
,
Program Chairs:
Jose L. Ayala
Federal University of Pernambuco, Brazil
,
Ken Stevens
University of Utah, USA

Copyright © 2011 ACM.

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Published: 02 May 2011

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GLSVLSI '11: Great Lakes Symposium on VLSI 2011

May 2 - 4, 2011

Lausanne, Switzerland

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Cited By

Suzuki DNatsui MHanyu T(2012)Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2012.6292025(334-337)Online publication date: Aug-2012
https://doi.org/10.1109/MWSCAS.2012.6292025

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