research-article

A design methodology for the automatic sizing of standard-cell libraries

Authors:

Christian Pilato,

Fabrizio Ferrandi,

Davide PandiniAuthors Info & Claims

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

Pages 151 - 156

https://doi.org/10.1145/1973009.1973040

Published: 02 May 2011 Publication History

Abstract

Current EDA tools are often based on standard-cell libraries for the design of modern complex systems-on-chip. In general, there are opposite trends to compact and extend the standard cell libraries, and to move towards custom libraries, highly optimized for specific goals (e.g., area, timing or power consumption) or designs. We thus propose a design methodology for library sizing that combines decimation strategies and generation of cell variants. The proposed methodology is based on Simulated Annealing, also integrating heuristic principles to efficiently guide the exploration process. The approach has been validated on a set of common benchmarks for logic synthesis, demonstrating interesting results, specially when starting from a relative small initial library.

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Cited By

Li YZhao JLiu YWang G(2023)A Comprehensive Study on the Design Methodology of Level Shifter CircuitsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.321398170:1(302-314)Online publication date: Jan-2023
https://doi.org/10.1109/TCSI.2022.3213981
Conceicao CPosser GReis R(2016)Reducing the number of transistors with gate clustering2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2016.7451035(163-166)Online publication date: Feb-2016
https://doi.org/10.1109/LASCAS.2016.7451035

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cover image ACM Conferences

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

May 2011

496 pages

ISBN:9781450306676

DOI:10.1145/1973009

General Chairs:
David Atienza
EPFL, Switzerland
,
Yuan Xie
Penn State University, USA
,
Program Chairs:
Jose L. Ayala
Federal University of Pernambuco, Brazil
,
Ken Stevens
University of Utah, USA

Copyright © 2011 ACM.

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Published: 02 May 2011

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GLSVLSI '11: Great Lakes Symposium on VLSI 2011

May 2 - 4, 2011

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Cited By

Li YZhao JLiu YWang G(2023)A Comprehensive Study on the Design Methodology of Level Shifter CircuitsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.321398170:1(302-314)Online publication date: Jan-2023
https://doi.org/10.1109/TCSI.2022.3213981
Conceicao CPosser GReis R(2016)Reducing the number of transistors with gate clustering2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2016.7451035(163-166)Online publication date: Feb-2016
https://doi.org/10.1109/LASCAS.2016.7451035

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