Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers
Pages 759 - 764
Abstract
A three-dimensional (3D) CMOS imager constructed from stacking a pixel array of image sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array is promising for high throughput imaging applications. The design specifications of the ADC array in the imager, which jointly and concurrently converts the pixel data to produce a final image, must consider both intra-ADC linearity and inter-ADC uniformity. In this paper, we investigate the relationship between the image quality and the linearity of individual ADCs as well as the uniformity of neighboring ADCs in the array. With the insights to this relationship, the specification requirements for the ADC array can be derived based on a desired level of image quality.
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Index Terms
- Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers
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Published In
June 2011
1055 pages
ISBN:9781450306362
DOI:10.1145/2024724
- General Chair:
- Leon Stok,
- Program Chairs:
- Nikil Dutt,
- Soha Hassoun
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Published: 05 June 2011
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