research-article

Compressor tree synthesis on commercial high-performance FPGAs

Authors:

Hadi Parandeh-Afshar,

Arkosnato Neogy,

Paolo IenneAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4, Issue 4

Article No.: 39, Pages 1 - 19

https://doi.org/10.1145/2068716.2068725

Published: 28 December 2011 Publication History

Abstract

Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. Compressor trees naturally occur in many DSP applications, such as FIR filters, and, in the more general case, their use can be maximized through the application of high-level transformations to arithmetically intensive data flow graphs. Due to the presence of carry-chains, it has long been thought that trees of 2- or 3-input carry-propagate adders are more efficient than compressor trees for FPGA synthesis; however, this is not the case. This article presents a heuristic for FPGA synthesis of compressor trees that outperforms adder trees and exploits carry-chains when possible. The experimental results show that, on average, the use of compressor trees can reduce critical path delay by 33% and 45% respectively, compared to adder trees synthesized on the Xilinx Virtex-5 and Altera Stratix III FPGAs.

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Cited By

Zuo DZhu JOuyang YMa Y(2025)RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space ReductionACM Transactions on Design Automation of Electronic Systems10.1145/3711850Online publication date: 14-Jan-2025
https://doi.org/10.1145/3711850
Opasatian AIkeda M(2025)Manipulated Lookup Table Method for Efficient High-Performance Modular MultiplierIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.350592033:1(114-127)Online publication date: 1-Jan-2025
https://dl.acm.org/doi/10.1109/TVLSI.2024.3505920
Hoßfeld KDamsgaard HNurmi JBlott MPreußer T(2024)High-efficiency Compressor Trees for Latest AMD FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/364509717:2(1-32)Online publication date: 10-Feb-2024
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Index Terms

Compressor tree synthesis on commercial high-performance FPGAs
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
2. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis
      1. Arbitrary-precision arithmetic
      2. Interval arithmetic

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cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 4, Issue 4

December 2011

179 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/2068716

Issue’s Table of Contents

Copyright © 2011 ACM.

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Association for Computing Machinery

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Publication History

Published: 28 December 2011

Accepted: 01 March 2011

Revised: 01 December 2010

Received: 01 June 2010

Published in TRETS Volume 4, Issue 4

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Cited By

Zuo DZhu JOuyang YMa Y(2025)RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space ReductionACM Transactions on Design Automation of Electronic Systems10.1145/3711850Online publication date: 14-Jan-2025
https://doi.org/10.1145/3711850
Opasatian AIkeda M(2025)Manipulated Lookup Table Method for Efficient High-Performance Modular MultiplierIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.350592033:1(114-127)Online publication date: 1-Jan-2025
https://dl.acm.org/doi/10.1109/TVLSI.2024.3505920
Hoßfeld KDamsgaard HNurmi JBlott MPreußer T(2024)High-efficiency Compressor Trees for Latest AMD FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/364509717:2(1-32)Online publication date: 10-Feb-2024
https://dl.acm.org/doi/10.1145/3645097
Böttcher AKumm M(2024)Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP61560.2024.00051(217-225)Online publication date: 24-Jul-2024
https://doi.org/10.1109/ASAP61560.2024.00051
Böttcher AKumm M(2024)Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs2024 IEEE 31st Symposium on Computer Arithmetic (ARITH)10.1109/ARITH61463.2024.00029(124-131)Online publication date: 10-Jun-2024
https://doi.org/10.1109/ARITH61463.2024.00029
Böttcher AKumm M(2023)Towards Globally Optimal Design of Multipliers for FPGAsIEEE Transactions on Computers10.1109/TC.2023.323812872:5(1261-1273)Online publication date: 1-May-2023
https://doi.org/10.1109/TC.2023.3238128
de Dinechin FKumm Mde Dinechin FKumm M(2023)Sums of Weighted BitsApplication-Specific Arithmetic10.1007/978-3-031-42808-1_7(151-201)Online publication date: 23-Aug-2023
https://doi.org/10.1007/978-3-031-42808-1_7
Tian MSima MMcGuire M(2022)Fixed–Point Arithmetic for Implementing Massive MIMO Systems2022 24th International Conference on Advanced Communication Technology (ICACT)10.23919/ICACT53585.2022.9728867(1-11)Online publication date: 13-Feb-2022
https://doi.org/10.23919/ICACT53585.2022.9728867
Christ MForget Lde Dinechin F(2022)Lossless Differential Table Compression for Hardware Function EvaluationIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.313140569:3(1642-1646)Online publication date: Mar-2022
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Bottcher AKumm Mde Dinechin F(2021)Resource Optimal Truncated Multipliers for FPGAs2021 IEEE 28th Symposium on Computer Arithmetic (ARITH)10.1109/ARITH51176.2021.00029(102-109)Online publication date: Jun-2021
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