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Communication visualization for bottleneck detection of high-level synthesis applications

Authors:

John Curreri,

Greg Stitt,

Alan GeorgeAuthors Info & Claims

FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

Pages 33 - 36

https://doi.org/10.1145/2145694.2145701

Published: 22 February 2012 Publication History

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Abstract

High-level synthesis tools increase FPGA productivity but can decrease performance compared to register-transfer level designs. To help optimize high-level synthesis applications, we introduce a bottleneck detection tool that provides a developer with a visualization of communication bandwidth between all application processes, while identifying potential bottlenecks via color coding. We evaluated the tool using third-party applications to identify and optimize bottlenecks in just several minutes, which achieved speedups ranging from 1.25x to 2.18x compared to the original FPGA execution. Overhead was modest with less than 2% resource overhead and 3% frequency overhead.

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Huthmann JPodobas ASommer LKoch ASano K(2020)Extending High-Level Synthesis with High-Performance Computing Performance Visualization2020 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER49012.2020.00047(371-380)Online publication date: Sep-2020
https://doi.org/10.1109/CLUSTER49012.2020.00047
Pham-Quoc CAl-Ars ZBertels K(2014)Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication ProfilingProceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops10.1109/IPDPSW.2014.21(151-160)Online publication date: 19-May-2014
https://dl.acm.org/doi/10.1109/IPDPSW.2014.21
Nilakantan SHempstead M(2013)Platform-independent analysis of function-level communication in workloads2013 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2013.6704685(196-206)Online publication date: Sep-2013
https://doi.org/10.1109/IISWC.2013.6704685

Index Terms

Communication visualization for bottleneck detection of high-level synthesis applications
1. Hardware
  1. Hardware validation
    1. Functional verification

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Published In

FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

February 2012

352 pages

ISBN:9781450311557

DOI:10.1145/2145694

General Chair:
Katherine Compton
University of Wisconsin-Madison
,
Program Chair:
Brad Hutchings
Brigham Young University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 22 February 2012

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FPGA '12: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2012

California, Monterey, USA

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FPGA '12 Paper Acceptance Rate 20 of 87 submissions, 23%;

Overall Acceptance Rate 125 of 627 submissions, 20%

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Huthmann JPodobas ASommer LKoch ASano K(2020)Extending High-Level Synthesis with High-Performance Computing Performance Visualization2020 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER49012.2020.00047(371-380)Online publication date: Sep-2020
https://doi.org/10.1109/CLUSTER49012.2020.00047
Pham-Quoc CAl-Ars ZBertels K(2014)Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication ProfilingProceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops10.1109/IPDPSW.2014.21(151-160)Online publication date: 19-May-2014
https://dl.acm.org/doi/10.1109/IPDPSW.2014.21
Nilakantan SHempstead M(2013)Platform-independent analysis of function-level communication in workloads2013 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2013.6704685(196-206)Online publication date: Sep-2013
https://doi.org/10.1109/IISWC.2013.6704685

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Layout-driven RTL binding techniques for high-level synthesis

An Introduction to High-Level Synthesis

Resource budgeting for Multiprocess High-level synthesis

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Recommendations

Layout-driven RTL binding techniques for high-level synthesis

An Introduction to High-Level Synthesis

Resource budgeting for Multiprocess High-level synthesis

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