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Automatic layout synthesis of leaf cells

Authors:

Sanjay Rekhi,

J. Donald Trotter,

Daniel H. LinderAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 267 - 272

https://doi.org/10.1145/217474.217540

Published: 01 January 1995 Publication History

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Cited By

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Ryzhenko NBurns SGroeneveld PSciuto DHassoun S(2012)Standard cell routing via boolean satisfiabilityProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228470(603-612)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228470
Okada KYamanouchi TKambe TYoshida K(2000)A cell synthesis method for salicide processProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368777(517-522)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368777
Serdar TSechen CWhite JSentovich E(1999)AKORDProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.339584(91-97)Online publication date: 7-Nov-1999
https://dl.acm.org/doi/10.5555/339492.339584
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Index Terms

Automatic layout synthesis of leaf cells
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Integrated circuits
    1. Logic circuits
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory

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Integration of behavioral and layout synthesis: a chip synthesis approach
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DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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Ryzhenko NBurns SGroeneveld PSciuto DHassoun S(2012)Standard cell routing via boolean satisfiabilityProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228470(603-612)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228470
Okada KYamanouchi TKambe TYoshida K(2000)A cell synthesis method for salicide processProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368777(517-522)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368777
Serdar TSechen CWhite JSentovich E(1999)AKORDProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.339584(91-97)Online publication date: 7-Nov-1999
https://dl.acm.org/doi/10.5555/339492.339584
Serdar TSechen C(1999)AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)10.1109/ICCAD.1999.810628(91-97)Online publication date: 1999
https://doi.org/10.1109/ICCAD.1999.810628
Saika SFukui MShinomiya NAkino T(1997)A two-dimensional transistor placement for cell synthesisProceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1997.600335(557-562)Online publication date: 1997
https://doi.org/10.1109/ASPDAC.1997.600335

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An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis

Integration of behavioral and layout synthesis: a chip synthesis approach

Layout synthesis of nmos gate-cells

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An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis

Integration of behavioral and layout synthesis: a chip synthesis approach

Layout synthesis of nmos gate-cells

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