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Cited By

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Sawasaki MYkman-Couvreur CLin B(2006)Externally hazard-free implementations of asynchronous control circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.64460716:8(835-848)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.644607
Khan ACeglarek DNi J(1998)Sensor Location Optimization for Fault Diagnosis in Multi-Fixture Assembly SystemsJournal of Manufacturing Science and Engineering10.1115/1.2830221120:4(781)Online publication date: 1998
https://doi.org/10.1115/1.2830221
Petrenko AYevtushenko N(1998)Solving asynchronous equationsFormal Description Techniques and Protocol Specification, Testing and Verification10.1007/978-0-387-35394-4_15(231-247)Online publication date: 1998
https://doi.org/10.1007/978-0-387-35394-4_15

Index Terms

Hierarchical optimization of asynchronous circuits
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
    2. Logic synthesis
      1. Circuit optimization

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DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

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Sawasaki MYkman-Couvreur CLin B(2006)Externally hazard-free implementations of asynchronous control circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.64460716:8(835-848)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.644607
Khan ACeglarek DNi J(1998)Sensor Location Optimization for Fault Diagnosis in Multi-Fixture Assembly SystemsJournal of Manufacturing Science and Engineering10.1115/1.2830221120:4(781)Online publication date: 1998
https://doi.org/10.1115/1.2830221
Petrenko AYevtushenko N(1998)Solving asynchronous equationsFormal Description Techniques and Protocol Specification, Testing and Verification10.1007/978-0-387-35394-4_15(231-247)Online publication date: 1998
https://doi.org/10.1007/978-0-387-35394-4_15

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Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Stored State Asynchronous Sequential Circuits

An optimization algorithm of hierarchical circuits

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Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Stored State Asynchronous Sequential Circuits

An optimization algorithm of hierarchical circuits

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