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A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation

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Madhav P. DesaiAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 125 - 130

https://doi.org/10.1145/240518.240542

Published: 01 June 1996 Publication History

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Nepal KSong HBahar RGrodstein JGarrett DLach JZukowski C(2004)RESTAProceedings of the 14th ACM Great Lakes symposium on VLSI10.1145/988952.989050(407-412)Online publication date: 26-Apr-2004
https://dl.acm.org/doi/10.1145/988952.989050
McMurchie LSechen CPileggi LKuehlmann A(2002)WTAProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774665(625-631)Online publication date: 10-Nov-2002
https://dl.acm.org/doi/10.1145/774572.774665
McDonald CBryant RRabaey J(2001)Computing logic-stage delays using circuit simulation and symbolic elmore analysisProceedings of the 38th annual Design Automation Conference10.1145/378239.378486(283-288)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.378486
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Index Terms

A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Nepal KSong HBahar RGrodstein JGarrett DLach JZukowski C(2004)RESTAProceedings of the 14th ACM Great Lakes symposium on VLSI10.1145/988952.989050(407-412)Online publication date: 26-Apr-2004
https://dl.acm.org/doi/10.1145/988952.989050
McMurchie LSechen CPileggi LKuehlmann A(2002)WTAProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774665(625-631)Online publication date: 10-Nov-2002
https://dl.acm.org/doi/10.1145/774572.774665
McDonald CBryant RRabaey J(2001)Computing logic-stage delays using circuit simulation and symbolic elmore analysisProceedings of the 38th annual Design Automation Conference10.1145/378239.378486(283-288)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.378486
Savithri SBlaauw D(1999)A three-tier assertion technique for SPICE verification of transistor level timing analysisProceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)10.1109/ICVD.1999.745145(175-180)Online publication date: 1999
https://doi.org/10.1109/ICVD.1999.745145
Nassif NDesai MHall DChawla BBryant RRabaey J(1998)Robust Elmore delay models suitable for full chip timing verification of a 600MHz CMOS microprocessorProceedings of the 35th annual Design Automation Conference10.1145/277044.277104(230-235)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277104
Shriver EHall DNassif NRahman NRethman NWatt GFarrell J(1998)Timing verification of the 21264: A 600 MHz full-custom microprocessorProceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)10.1109/ICCD.1998.727029(96-103)Online publication date: 1998
https://doi.org/10.1109/ICCD.1998.727029

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Path sensitization in critical path problem [logic circuit design]

Efficient logic-level timing analysis using constraint-guided critical path search

Parameterized Critical Path Selection for Delay Fault Testing

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Path sensitization in critical path problem [logic circuit design]

Efficient logic-level timing analysis using constraint-guided critical path search

Parameterized Critical Path Selection for Delay Fault Testing

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