Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/240518.240569acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article
Free access

Area efficient pipelined pseudo-exhaustive testing with retiming

Published: 01 June 1996 Publication History
First page of PDF

References

[1]
C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry", Algorithmica, vol. 6, no. 1, 1991, pp.5-35.
[2]
D. Kagaris and S. Tragoudas, "Partial Scan with Retiming", Proc. 30th ACM/IEEE DAC, June 1993, pp. 249-254.
[3]
S.T. Chakradhar and Suji Dey, "Resynthesis and Retiming for Optimum Partial Scan", Proc. 31st ACM/IEEE DAC, June 1994, pp. 87-93.
[4]
H. Y. Liou, T. Y. Lin, C. K. Cheng and L. T. Liu, "Circuit Partitioning for Pipelined Pseudo-Exhaustive Testing Using Simulated Annealing", Proc. IEEE Custom Integrated Circuits Conference, May 1994, pp. 417-20.
[5]
F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits", Proc. IEEE ISCAS, 1989, pp. 1929-34.
[6]
C.W. Yeh, C. K. Cheng, and T. Y. Lin, "A General Purpose Multiple-Way Partitioning Algorithm", Proc. 28th ACM/ IEEE DAC, June 1991, pp. 421-425.
[7]
E. Wu, "A Tool for Implementing Pseudo-exhaustive Selftest", AT&T Tech. Journal, Jan. 1991, pp. 87-100.
[8]
T.Y. Lin and H. Y. Liou, "A New Framework for Designing BIT Multichip Modules with Pipelined Test Strategy", IEEE D&T, vol. 10, no. 4, Dec. 1993, pp. 38-51.
[9]
R. Tarjan, "Depth-first Search and Linear Graph Algorithms", SIAM J. Computing, June 1972, vol.1, no.2, pp. 146-60.
[10]
C. W. Yeh, C. K. Cheng, and T. Y. Lin, "A Probabilistic Multicommodity-flow Solution to Circuit Clustering Problems", Proc. ICCAD, Nov. 1992, pp. 428-31.
[11]
T. H. Cormen, C. E. Leiserson, and R. L. Rivest, "Introduction to Algorithms", MIT Press, Cambridge, Ma., 1990.
[12]
S. Sastry, and A. Majumdar, "Test Efficiency Analysis of Random Self-Test of Sequential Circuits", IEEE Trans. on CAD, vol. 10, no. 3, Mar. 1991, pp. 390-398.
[13]
R. Srinivasan, S. K. Gupta and M. A. Breuer, "An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing", Proc. 30th IEEE Design Automation Conference, June, 1993, pp. 525- 530.
[14]
R. L. Geiger, E E. Allen, and N. R. Strader, "VLSI Design Techniques for Analog and Digital Circuits", McGraw-Hill, 1990.
[15]
H. Y. Liou, T. Y. Lin, and C. K. Cheng, "A Study of Pipelined Pseudo-Exhaustive Testing on VLSI Circuits with Feedback", Proc. of ASIC'94, Sep. 1994, pp. 421-425.
[16]
H. J. Trouati and R. K. Brayton, "Computing the Initial States of Retimed Circuits", IEEE Trans. on CAD, vol. 12, no. 1, Jan. 1993, pp. 157-162.

Cited By

View all
  • (2001)Layout aware retimingProceedings of the 11th Great Lakes symposium on VLSI10.1145/368122.368153(25-30)Online publication date: 1-Mar-2001

Index Terms

  1. Area efficient pipelined pseudo-exhaustive testing with retiming

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      DAC '96: Proceedings of the 33rd annual Design Automation Conference
      June 1996
      839 pages
      ISBN:0897917790
      DOI:10.1145/240518
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 01 June 1996

      Permissions

      Request permissions for this article.

      Check for updates

      Qualifiers

      • Article

      Conference

      DAC96
      Sponsor:
      DAC96: The 33rd Design Automation Conference
      June 3 - 7, 1996
      Nevada, Las Vegas, USA

      Acceptance Rates

      DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;
      Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

      Upcoming Conference

      DAC '25
      62nd ACM/IEEE Design Automation Conference
      June 22 - 26, 2025
      San Francisco , CA , USA

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)37
      • Downloads (Last 6 weeks)12
      Reflects downloads up to 12 Nov 2024

      Other Metrics

      Citations

      Cited By

      View all
      • (2001)Layout aware retimingProceedings of the 11th Great Lakes symposium on VLSI10.1145/368122.368153(25-30)Online publication date: 1-Mar-2001

      View Options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Get Access

      Login options

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media