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Innovative verification strategy reduces design cycle time for high-end SPARC processor

Published: 01 June 1996 Publication History
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    • (2012)Checking architectural outputs instruction-by-instruction on acceleration platformsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228531(955-961)Online publication date: 3-Jun-2012
    • (2001)A transaction-based unified simulation/emulation architecture for functional verificationProceedings of the 38th annual Design Automation Conference10.1145/378239.379036(623-628)Online publication date: 22-Jun-2001
    • (1999)Verification of a microprocessor using real world applicationsProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.311478(181-184)Online publication date: 1-Jun-1999
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      cover image ACM Conferences
      DAC '96: Proceedings of the 33rd annual Design Automation Conference
      June 1996
      839 pages
      ISBN:0897917790
      DOI:10.1145/240518
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      New York, NY, United States

      Publication History

      Published: 01 June 1996

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      DAC96: The 33rd Design Automation Conference
      June 3 - 7, 1996
      Nevada, Las Vegas, USA

      Acceptance Rates

      DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;
      Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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      Cited By

      View all
      • (2012)Checking architectural outputs instruction-by-instruction on acceleration platformsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228531(955-961)Online publication date: 3-Jun-2012
      • (2001)A transaction-based unified simulation/emulation architecture for functional verificationProceedings of the 38th annual Design Automation Conference10.1145/378239.379036(623-628)Online publication date: 22-Jun-2001
      • (1999)Verification of a microprocessor using real world applicationsProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.311478(181-184)Online publication date: 1-Jun-1999
      • (1999)Verification of a microprocessor using real world applicationsProceedings 1999 Design Automation Conference (Cat. No. 99CH36361)10.1109/DAC.1999.781306(181-184)Online publication date: 1999
      • (1998)Virtual chipProceedings of the 35th annual Design Automation Conference10.1145/277044.277084(170-173)Online publication date: 1-May-1998
      • (1997)Practical concurrent ASIC and system design and verificationProceedings of the 1997 European conference on Design and Test10.5555/787260.787719Online publication date: 17-Mar-1997
      • (1997)A C-based RTL design verification methodology for complex microprocessorProceedings of the 34th annual Design Automation Conference10.1145/266021.266040(83-88)Online publication date: 13-Jun-1997
      • (1997)Practical concurrent ASIC and system design and verificationProceedings European Design and Test Conference. ED & TC 9710.1109/EDTC.1997.582412(532-536)Online publication date: 1997
      • (1997)A C-based RTL Design Verification Methodology For Complex MicroprocessorProceedings of the 34th Design Automation Conference10.1109/DAC.1997.597122(83-88)Online publication date: 1997
      • (1996)Generation of test cases for hardware design verification of a super-scalar Fetch ProcessorProceedings International Test Conference 1996. Test and Design Validity10.1109/TEST.1996.557152(904-913)Online publication date: 1996

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