Article

A transaction-based unified simulation/emulation architecture for functional verification

Authors:

Murali Kudlugi,

Soha Hassoun,

Charles Selvidge,

Duaine PryorAuthors Info & Claims

DAC '01: Proceedings of the 38th annual Design Automation Conference

Pages 623 - 628

https://doi.org/10.1145/378239.379036

Published: 22 June 2001 Publication History

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Abstract

A transaction-based layered architecture providing for 100% portability of a C-based testbench between simulation and emulation is proposed. Transaction-based communication results in performance which is commensurate with emulation without a hardware target. Testbench portability eliminates duplicated effort when combining system level simulation and emulation. An implementation based on the IKOS VStation emulator validates these architectural claims on real designs.

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Cited By

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Khan HKamal AGoehringer D(2018)An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded ProcessorsApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_35(433-445)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_35
Banerjee SGupta T(2014)Optimized Simulation Acceleration with Partial Testbench EvaluationProceedings of the 2014 15th International Microprocessor Test and Verification Workshop10.1109/MTV.2014.19(22-27)Online publication date: 15-Dec-2014
https://dl.acm.org/doi/10.1109/MTV.2014.19
Kornaros GChristoforakis IAstrinaki M(2012)An automated infrastructure for real-time monitoring of multi-core Systems-on-Chip2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2012.6219025(56-61)Online publication date: Apr-2012
https://doi.org/10.1109/DDECS.2012.6219025
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A transaction-based unified simulation/emulation architecture for functional verification

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Published In

DAC '01: Proceedings of the 38th annual Design Automation Conference

June 2001

863 pages

ISBN:1581132972

DOI:10.1145/378239

Chairman:
Jan Rabaey
Univ. of California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 22 June 2001

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Khan HKamal AGoehringer D(2018)An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded ProcessorsApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_35(433-445)Online publication date: 8-Apr-2018
Banerjee SGupta T(2014)Optimized Simulation Acceleration with Partial Testbench EvaluationProceedings of the 2014 15th International Microprocessor Test and Verification Workshop10.1109/MTV.2014.19(22-27)Online publication date: 15-Dec-2014
Kornaros GChristoforakis IAstrinaki M(2012)An automated infrastructure for real-time monitoring of multi-core Systems-on-Chip2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2012.6219025(56-61)Online publication date: Apr-2012
Sung WOu SLiu YChen C(2012)Employed VeriLite simulation to improve SOC design and verificationComputer Applications in Engineering Education10.1002/cae.2040420:2(374-382)Online publication date: 11-Apr-2012
Brandner FHorspool NKrall A(2010)DSP Instruction Set SimulationHandbook of Signal Processing Systems10.1007/978-1-4419-6345-1_24(679-705)Online publication date: 16-Jul-2010
Katona MDjukaric DCvejanovic D(2009)Multiple Scenario Approach for Pre-Silicon Hardware/Software Co-VerificationProceedings of the 2009 First IEEE Eastern European Conference on the Engineering of Computer Based Systems10.1109/ECBS-EERC.2009.10(110-119)Online publication date: 7-Sep-2009
Cong JGururaj KHan GKaplan ANaik MReinman GNassif SRoychowdhury J(2008)MC-SimProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509541(364-371)Online publication date: 10-Nov-2008
Shim KPark CYang S(2007)Efficient Simulation Acceleration by FPGA Compilation AvoidanceThe KIPS Transactions:PartA10.3745/KIPSTA.2007.14-A.3.14114A:3(141-146)Online publication date: 30-Jun-2007
Asadi GMiremadi SEjlali A(2007)Fast co-verification of HDL modelsMicroelectronic Engineering10.1016/j.mee.2006.02.00784:2(218-228)Online publication date: 1-Feb-2007
Hauck SDeHon A(2007)Reconfigurable ComputingundefinedOnline publication date: 2-Nov-2007
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An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

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A transaction-based unified architecture for simulation and emulation

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

Symbiotic Network Simulation and Emulation

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