research-article

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing

Authors:

Cheng-Kok KohAuthors Info & Claims

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

Pages 713 - 719

https://doi.org/10.1145/2429384.2429539

Published: 05 November 2012 Publication History

Abstract

Considering routability issue in the early stages of VLSI design flow can avoid generating an unroutable design. Several recent routablity-driven placers [8--11] adopt a built-in global router to estimate routing congestion. While the routability of the placement solution improves, the performance of these placers degrades. Many of these built-in global router and state-of-the-art academic global routers use maze routing to seek a detoured path. Although very effective, maze routing is relatively slower than other routing algorithms, such as pattern routing and monotonic routing algorithms. This work presents two efficient routing algorithms, called unilateral monotonic routing and hybrid unilateral monotonic routing, to replace maze routing and to realize a highly fast maze-free global router that is suited to act as a built-in routing congestion estimator for placers. Experimental results indicate that RCE achieves similar routing quality when compared with [20], as well as an over 20-fold runtime speedup in large benchmarks.

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Cited By

Qi ZPeng QHu SYou H(2024)Effective Heterogeneous Graph Neural Network for Routing Congestion Prediction2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617734(369-373)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617734
Zhou ZPan YLemieux GIvanov A(2023)MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global RoutingACM Transactions on Design Automation of Electronic Systems10.1145/359076828:5(1-25)Online publication date: 9-Sep-2023
https://dl.acm.org/doi/10.1145/3590768
Jiang YFang S(2023)COALA: Concurrently Assigning Wire Segments to Layers for 2-D Global RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317835342:2(569-582)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3178353
Show More Cited By

Index Terms

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Hardware validation

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cover image ACM Conferences

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

November 2012

781 pages

ISBN:9781450315739

DOI:10.1145/2429384

General Chair:
Alan J. Hu
Univ. of British Columbia, Vancouver, BC, Canada

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2012

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ICCAD '12

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SIGDA

ICCAD '12: The International Conference on Computer-Aided Design

November 5 - 8, 2012

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Qi ZPeng QHu SYou H(2024)Effective Heterogeneous Graph Neural Network for Routing Congestion Prediction2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617734(369-373)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617734
Zhou ZPan YLemieux GIvanov A(2023)MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global RoutingACM Transactions on Design Automation of Electronic Systems10.1145/359076828:5(1-25)Online publication date: 9-Sep-2023
https://dl.acm.org/doi/10.1145/3590768
Jiang YFang S(2023)COALA: Concurrently Assigning Wire Segments to Layers for 2-D Global RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317835342:2(569-582)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3178353
Chen YSu MDing HWeng SLin ZBai X(2023)High-correlation 3D routability estimation for congestion-guided global routingThe Journal of Supercomputing10.1007/s11227-023-05553-080:3(3114-3141)Online publication date: 29-Aug-2023
https://doi.org/10.1007/s11227-023-05553-0
Su MDing HWeng SZou CZhou ZChen YChen JChang YWang T(2022)High-Correlation 3D Routability Estimation for Congestion-Guided Global RoutingProceedings of the 27th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC52403.2022.9712517(580-585)Online publication date: 17-Jan-2022
https://dl.acm.org/doi/10.1109/ASP-DAC52403.2022.9712517
Lin YGuo ZMai J(2022)Deep Learning Framework for PlacementMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_9(221-245)Online publication date: 10-Aug-2022
https://doi.org/10.1007/978-3-031-13074-8_9
Huang YLin CLiang WChen H(2021)Learning Based Placement Refinement to Reduce DRC Short Violations2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VLSI-DAT52063.2021.9427321(1-4)Online publication date: 19-Apr-2021
https://doi.org/10.1109/VLSI-DAT52063.2021.9427321
Wu WDi ZShi JFeng QTang Z(2020)A local congestion elimination technique driven by overflowIEICE Electronics Express10.1587/elex.17.20200232Online publication date: 2020
https://doi.org/10.1587/elex.17.20200232
Hung JHuang SCheng CKao HCheng W(2020)Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers2020 IEEE 38th VLSI Test Symposium (VTS)10.1109/VTS48691.2020.9107604(1-6)Online publication date: Apr-2020
https://doi.org/10.1109/VTS48691.2020.9107604
Zhu WZhang XLiu GGuo WWang T(2020)MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VLSI-DAT49148.2020.9196219(1-4)Online publication date: Aug-2020
https://doi.org/10.1109/VLSI-DAT49148.2020.9196219
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