Clock distribution networks consume a significant portion of on-chip power. Traditional buffered clock distribution power is limited by frequency, capacitance, and activity rates. Resonant clock distributions can reduce this power by "recycling" energy ...

Recent interest in approximate computation is driven by its potential to achieve large energy savings. This paper formally demonstrates an optimal way to reduce energy via voltage over-scaling at the cost of errors due to timing starvation in addition. ...

Spin-transfer torque random access memory (STT-RAM) has recently gained increased attentions from circuit design and architecture societies. Although STT-RAM offers a good combination of small cell size, nanosecond access time and non-volatility for ...

Considering routability issue in the early stages of VLSI design flow can avoid generating an unroutable design. Several recent routablity-driven placers [8--11] adopt a built-in global router to estimate routing congestion. While the routability of the ...

In 3D-IC integration and its implied resource optimization, a particularly critical resource is deadspace --- regions between floorplan blocks. Deadspace is required for through-silicon via (TSV) planning and other related design tasks, but the ...

Voltage partitioning on functional units/blocks targeting peak power minimization has been demonstrated to be effective for energy reduction considering voltage island shutdown impact. However, the existing technique can only solve this NP-hard problem ...

A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of ...

OLED (Organic Light Emitting Diode) technology has already been adopted in many modern smart mobile devices, including cellphones, tablets, laptop etc. However, the power dissipation of displays in some applications like real-time video streaming, ...

A modern smartphone or tablet-PC is typically equipped a high-resolution and large-size display, which is a primary power consumer. In spite of the relatively high power efficiency of organic light emitting diode (OLED) displays, the integrated display ...

Following the advent of the digital multi-media era and the popularity of the internet, high-resolution flat-panel displays (FPDs) are becoming the central feature of many consumer products, from camcorders, mobile/smart phones, to notebook PCs. The FPD ...

The power distribution network of an integrated circuit must be checked throughout the design process to ensure that supply voltage fluctuations do not exceed certain critical thresholds. One way of doing this is by simulation, which requires knowledge ...

This paper is intended to give a brief tutorial understanding of on-die power grid effects. Board, package and on-die power grids deliver power to a die having both global (full-die) as well as local (intra-die) transient effects. With a simple ...

Power delivery design plays a critical role in ensuring power delivery integrity and achieving overall design power efficiency. A power delivery network (PDN) consists of a multiplicity of passive and active components, which interact with each other in ...

In this paper, we propose PGT_SOLVER - an effecient solver for power grid transient analysis. It is based on direct solver. The conductance matrix is SPD and is generated by modifying the matrix for DC analysis. Modified sparse vector technique is ...

Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield ...

In this paper, we present a novel configurable analog routing methodology for more efficient analog layout automation. By the help of OpenAccess constraint group format, the technology process rules and analog layout design intention/constraints are ...

Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-...

Deriving a circuit for a Boolean function or improving an available circuit are typical tasks solved by logic synthesis. Numerous algorithms in this area have been proposed and implemented over the last 50 years. This paper presents a "lazy" approach to ...

By allowing the occurrence of infrequent timing errors and correcting them with rollback mechanisms, the so-called timing speculation (TS) technique can significantly improve circuit energy-efficiency and hence has become one of the most promising ...

High assurance systems require strict guarantees on information flow security and fault tolerance or else face catastrophic consequences. Recently, Gate Level Information Flow Tracking (GLIFT) has been proposed to monitor information flows at the level ...