research-article

On logic synthesis for timing speculation

Authors:

Qiang XuAuthors Info & Claims

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

Pages 591 - 596

https://doi.org/10.1145/2429384.2429512

Published: 05 November 2012 Publication History

Abstract

By allowing the occurrence of infrequent timing errors and correcting them with rollback mechanisms, the so-called timing speculation (TS) technique can significantly improve circuit energy-efficiency and hence has become one of the most promising solutions to mitigate the ever-increasing variation effects in nanometer technologies. As timing error recovery incurs non-trivial performance/energy overhead, it is important to reshape the delay distribution of critical paths in timing-speculated circuits to minimize their timing error rates. Most existing TS optimization techniques achieve this objective with post-synthesis techniques such as gate sizing or body biasing. In this work, we propose to conduct logic synthesis for timing-speculated circuits from the ground up. Being able to manipulate circuit structures during logic optimization, the proposed solution is able to dramatically reduce circuit timing error rates and hence improve its throughput, as demonstrated with experimental results on various benchmark circuits.

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Cited By

Tahoori MGolanbari M(2020)Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data PathsJournal of Low Power Electronics and Applications10.3390/jlpea1004004210:4(42)Online publication date: 3-Dec-2020
https://doi.org/10.3390/jlpea10040042
Cheng HWang HZhang MHand DBeerel P(2019)Automatic Retiming of Two-Phase Latch-Based Resilient CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284663138:7(1305-1316)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2846631
Alan THenkel J(2018)SlackHammer: Logic Synthesis for Graceful Errors Under Frequency ScalingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285836437:11(2802-2811)Online publication date: Nov-2018
https://doi.org/10.1109/TCAD.2018.2858364
Show More Cited By

Index Terms

On logic synthesis for timing speculation
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits

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Published In

cover image ACM Conferences

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

November 2012

781 pages

ISBN:9781450315739

DOI:10.1145/2429384

General Chair:
Alan J. Hu
Univ. of British Columbia, Vancouver, BC, Canada

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2012

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Research-article

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Research Grants Council, University Grants Committee, Hong Kong

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ICCAD '12

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SIGDA

ICCAD '12: The International Conference on Computer-Aided Design

November 5 - 8, 2012

California, San Jose

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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ICCAD '24

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IEEE/ACM International Conference on Computer-Aided Design

October 27 - 31, 2024

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Cited By

Tahoori MGolanbari M(2020)Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data PathsJournal of Low Power Electronics and Applications10.3390/jlpea1004004210:4(42)Online publication date: 3-Dec-2020
https://doi.org/10.3390/jlpea10040042
Cheng HWang HZhang MHand DBeerel P(2019)Automatic Retiming of Two-Phase Latch-Based Resilient CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284663138:7(1305-1316)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2846631
Alan THenkel J(2018)SlackHammer: Logic Synthesis for Graceful Errors Under Frequency ScalingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285836437:11(2802-2811)Online publication date: Nov-2018
https://doi.org/10.1109/TCAD.2018.2858364
Huang HCheng HChu CBeerel P(2018)Area Optimization of Timing Resilient Designs Using ResynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.274800137:6(1197-1210)Online publication date: Jun-2018
https://doi.org/10.1109/TCAD.2017.2748001
Han QXu QJone W(2018)SERAIntegration, the VLSI Journal10.1016/j.vlsi.2017.08.00760:C(1-12)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2017.08.007
Lin CWan LChen D(2017)C-MineACM Transactions on Design Automation of Electronic Systems10.1145/314453423:2(1-23)Online publication date: 29-Nov-2017
https://dl.acm.org/doi/10.1145/3144534
Wang HZhang MBeerel P(2017)Retiming of Two-Phase Latch-Based Resilient CircuitsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062312(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062312
Huang HCheng HChu CBeerel P(2016)Area optimization of resilient designs guided by a mixed integer geometric programProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897990(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2897990
Yazdanbakhsh AMahajan DThwaites BPark JNagendrakumar ASethuraman SRamkrishnan KRavindran NJariwala RRahimi AEsmaeilzadeh HBazargan KNebel WAtienza D(2015)AxilogProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755938(812-817)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755938
Ye RYuan FZhang JXu QNebel WAtienza D(2015)On the premises and prospects of timing speculationProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755890(605-608)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755890
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