research-article

High-performance, low-power resonant clocking

Authors:

Matthew R. Guthaus,

Baris TaskinAuthors Info & Claims

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

Pages 742 - 745

https://doi.org/10.1145/2429384.2429545

Published: 05 November 2012 Publication History

Abstract

Clock distribution networks consume a significant portion of on-chip power. Traditional buffered clock distribution power is limited by frequency, capacitance, and activity rates. Resonant clock distributions can reduce this power by "recycling" energy on-chip and reducing the overall clock power. This tutorial introduces recent techniques for distributed-LC, traveling wave, and standing wave resonant clock distributions. In particular, the tutorial discusses the recent developments and open research problems. The tutorial covers both circuits, computer-aided design algorithms and methodologies for resonant clocking.

References

[1]

S. Chan, P. Restle, K. Shepard, N. James, and R. Franch. A 4.6GHz resonant global clock distribution network. In IEEE International Solid-State Circuits Conference (ISSCC), pages 342--343, February 2004.

[2]

S. C. Chan, K. L. Shepard, and P. J. Restle. Design of resonant global clock distributions. In International Conference on Computer Design (ICCD), pages 248--253, October 2003.

Digital Library

[3]

V. Chi. Salphasic distribution of clock signals for synchronous systems. IEEE Transactions on Computers, 43(5): 597--602, May 1994.

Digital Library

[4]

J.-Y. Chueh, M. Papaefthymiou, and C. Ziesler. Two-phase resonant clock distribution. In IEEE International Symposium on Very Large Scale Integration (ISVLSI), pages 65--70, May 2005.

Digital Library

[5]

W. Condley, X. Hu, and M. Guthaus. A methodology for local resonant clock synthesis using LC-assisted local clock buffers. In International Conference on Computer-Aided Design (ICCAD), pages 503--506, November 2011.

Digital Library

[6]

V. Cordero and S. Khatri. Clock distribution scheme using coplanar transmission lines. In IEEE Design, Automation and Test in Europe (DATE), pages 985--990, March 2008.

Digital Library

[7]

http://www.cyclos-semi.com.

[8]

A. Drake, K. Nowka, T. Nguyen, J. Burns, and R. Brown. Resonant clocking using distributed parasitic capacitance. IEEE Journal of Solid-State Circuits (JSSC), 39(9): 1520--1528, September 2004.

[9]

M. Guthaus, X. Hu, G. Wilke, G. Flache, and R. Reis. High-performance clock mesh optimization. ACM Transactions on Design Automation of Electronic Systems (TODAES), 17(3): 33:1--33:17, June 2012.

Digital Library

[10]

M. R. Guthaus. Distributed LC resonant clock tree synthesis. In IEEE International Symposium on Circuits and Systems (ISCAS), pages 1215--1218, May 2011.

[11]

M. R. Guthaus, G. Wilke, and R. Reis. Non-uniform clock mesh optimization with linear programming buffer insertion. In ACM/IEEE Design Automation Conference (DAC), pages 74--79, June 2010.

Digital Library

[12]

V. Honkote and B. Taskin. Custom rotary clock router. In International Conference on Computer Design (ICCD), pages 114--119, October 2008.

[13]

V. Honkote and B. Taskin. PEEC based parasitic modeling for power analysis on custom rotary rings. In Proceedings of the IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2010.

Digital Library

[14]

V. Honkote and B. Taskin. Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array. In Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2010.

[15]

V. Honkote and B. Taskin. CROA: Design and analysis of custom rotary oscillatory array. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(10): 1837--1847, October 2011.

Digital Library

[16]

V. Honkote and B. Taskin. ZeROA: Zero clock skew rotary oscillatory array. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(8): 1528--1532, August 2012.

Digital Library

[17]

X. Hu, W. Condley, and M. R. Guthaus. Library-aware resonant clock synthesis (LARCS). In ACM/IEEE Design Automation Conference (DAC), pages 145--150, June 2012.

Digital Library

[18]

X. Hu and M. Guthaus. Distributed LC resonant clock grid synthesis. IEEE Transactions on Circuits and Systems I (TCAS-I), 2012.

[19]

X. Hu and M. R. Guthaus. Distributed resonant clock grid synthesis (ROCKS). In ACM/IEEE Design Automation Conference (DAC), pages 516--521, June 2011.

Digital Library

[20]

J. Rosenfeld and E. Friedman. Design methodology for global resonant h-tree clock distribution networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(2): 135--148, February 2007.

Digital Library

[21]

J. Lu, V. Honkote, X. Chen, and B. Taskin. Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. In Proceedings of the Design, Automation and Test in Europe (DATE) Conference, pages 455--460, March 2011.

[22]

E. D. Marsman, R. M. Senger, M. S. McCorquodale, M. R. Guthaus, R. A. Ravindran, G. S. Dasinka, S. A. Mahlke, and R. B. Brown. A 16-bit low-power microcontroller with monolithic MEMS-LC clocking. In IEEE International Symposium on Circuits and Systems (ISCAS), pages 624--627, 2005.

[23]

http://www.multigig.com.

[24]

F. O'Mahony, C. Yue, M. Horowitz, and S. Wong. Design of a 10GHz clock distribution network using coupled standing-wave oscillators. In ACM/IEEE Design Automation Conference (DAC), pages 682--687, June 2003.

Digital Library

[25]

P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger, and A. Mule. The clock distribution of the POWER4 microprocessor. In IEEE International Solid-State Circuits Conference (ISSCC), pages 144--145, February 2002.

[26]

V. Sathe, S. Arekapudi, C. Ouyang, M. Papaefthymiou, A. Ishii, and S. Naffziger. Resonant clock design for a power-efficient high-volume x86-64 microprocessors. In IEEE International Solid-State Circuits Conference (ISSCC), pages 68--70, February 2012.

[27]

R. M. Senger, E. D. Marsman, M. S. McCorquodale, F. H. Gebara, K. L. Kraver, M. R. Guthaus, and R. B. Brown. A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. In ACM/IEEE Design Automation Conference (DAC), pages 520--525, June 2003.

Digital Library

[28]

K. Takinami, R. Strandberg, P. Liang, G. de Mercey, T. Wong, and M. Hassibi. A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOS. In IEEE International Solid-State Circuits Conference (ISSCC), pages 100--102, February 2012.

[29]

K. Takinami, R. Walsworth, S. Osman, and S. Beccue. Phase-noise analysis in rotary traveling-wave oscillators using simple physical model. IEEE Transactions on Microwave Theory and Techniques, 58(6): 1465--1474, June 2010.

[30]

B. Taskin, J. Demaio, O. Farell, M. Hazeltine, and R. Ketner. Custom topology rotary clock router with tree subnetworks. ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(3), May 2009. Article 44.

Digital Library

[31]

Y. Teng, J. Lu, and B. Taskin. Roa-brick topology for rotary resonant clocks. In Proceedings of the IEEE International Conference on Computer Design (ICCD), pages 273--278, October 2011.

Digital Library

[32]

Y. Teng and B. Taskin. Look-up table based low power rotary traelling wave oscillator design considering the skin effect. Journal of Low Power Electronics (JOLPE), 6(4): 1--12, December 2010.

[33]

Y. Teng and B. Taskin. Process variation sensitivity of the rotary traveling wave oscillator. In Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pages 236--242, March 2011.

[34]

Y. Teng and B. Taskin. Synchronization scheme for brick-based rotary oscillator arrays. In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 117--122, May 2012.

Digital Library

[35]

G. Venkataraman, J. Hu, F. Liu, and C. N. Sze. Integrated placement and skew optimization for rotary clocking. In IEEE Design, Automation and Test in Europe (DATE), pages 756--761, March 2006.

Digital Library

[36]

J. Wood, T. C. Edwards, and S. Lipa. Rotary traveling-wave oscillator arrays: A new clock technology. IEEE Journal of Solid-State Circuits (JSSC), 36(11): 1654--1664, November 2001.

[37]

Z. Yu and X. Liu. Implementing multiphase resonant clocking on a finite-impulse response filter. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(11): 1593--1601, November 2009.

Digital Library

[38]

Y. Zhang, J. F. Buckwalter, and C. Cheng. On-chip global clock distribution using directional rotary traveling-wave oscillator. In IEEE Electrical Performance of Electronic Packaging and and Systems (EPEPS), pages 251--254, October 2009.

[39]

C. Zhuo, H. Zhang, R. Samanta, J. Hu, and K. Chen. Modeling, optimization and control of rotary traveling-wave oscillator. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 476--480, November 2007.

Digital Library

[40]

C. Ziesler, S. Kim, and M. Papaefthymiou. A resonant clock generator for single-phase adiabatic systems. In IEEE International Symposium on Low Power Electronics and Design (ISLPED), pages 159--164, August 2001.

Digital Library

Cited By

Ichihashi MHarada SKanaya H(2019)3.3-mA 2.8-GHz Bufferless LC Oscillator Directly Driving a 10-mm on-chip Clock Distribution LineIEICE Electronics Express10.1587/elex.16.20190301Online publication date: 2019
https://doi.org/10.1587/elex.16.20190301
ICHIHASHI MKANAYA H(2018)A Low-Power and GHz-Band LC-DCO Directly Drives 10mm On-Chip Clock Distribution Line in 0.18µm CMOSIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E101.A.1907E101.A:11(1907-1914)Online publication date: 1-Nov-2018
https://doi.org/10.1587/transfun.E101.A.1907
Zhang WHu YCui KWang LZheng L(2016)Design of a standing wave oscillator based PLL2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS.2016.7804038(559-562)Online publication date: Oct-2016
https://doi.org/10.1109/APCCAS.2016.7804038
Show More Cited By

Index Terms

High-performance, low-power resonant clocking
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

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Published In

cover image ACM Conferences

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

November 2012

781 pages

ISBN:9781450315739

DOI:10.1145/2429384

General Chair:
Alan J. Hu
Univ. of British Columbia, Vancouver, BC, Canada

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2012

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Division of Computing and Communication Foundations

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ICCAD '12

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SIGDA

ICCAD '12: The International Conference on Computer-Aided Design

November 5 - 8, 2012

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Ichihashi MHarada SKanaya H(2019)3.3-mA 2.8-GHz Bufferless LC Oscillator Directly Driving a 10-mm on-chip Clock Distribution LineIEICE Electronics Express10.1587/elex.16.20190301Online publication date: 2019
https://doi.org/10.1587/elex.16.20190301
ICHIHASHI MKANAYA H(2018)A Low-Power and GHz-Band LC-DCO Directly Drives 10mm On-Chip Clock Distribution Line in 0.18µm CMOSIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E101.A.1907E101.A:11(1907-1914)Online publication date: 1-Nov-2018
https://doi.org/10.1587/transfun.E101.A.1907
Zhang WHu YCui KWang LZheng L(2016)Design of a standing wave oscillator based PLL2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS.2016.7804038(559-562)Online publication date: Oct-2016
https://doi.org/10.1109/APCCAS.2016.7804038
Guthaus MWilke GReis R(2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442102

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