Cited By
View all- Liu RTang YFang B(2014)Topological Coding and Its Application in the Refinement of SIFTIEEE Transactions on Cybernetics10.1109/TCYB.2014.230179744:11(2155-2166)Online publication date: Nov-2014
A memory-efficient hardware architecture for real-time feature detection of the SIFT algorithm (abstract only)
Authors: 
Wenjuan Deng, Yiqun ZhuAuthors Info & Claims
Wenjuan Deng, Yiqun ZhuAuthors Info & ClaimsPage 273
Abstract
The SIFT (Scale Invariant Feature Transform) is a most popular image processing algorithm that has been widely used in solving image matching related problems. However, SIFT is of high computational complexity and large memory requirement that prevent it from being applied to applications that are unable to offer large on-chip memory. Based on the analysis of the memory requirement of SIFT feature detection, a novel memory access strategy is proposed to reduce the hardware memory usage. In addition, to achieve real-time performance of high resolution video streams, dedicated hardware architecture with multi-pixel based processing scheme has been developed. Compared with conventional designs, our design achieves hardware memory reduction of at least 58.8%.
References
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D. G. Lowe, "Distinctive image features from scale-invariant keypoints," Int. J. Computer Vision. vol. 60, no. 2, pp. 91--110, Jan. 2004.
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D. Chati, F. Muhlbauer, T. Braun, C. Bobda, and K. Berns, "Hardware/software co-design of a key point detector on FPGA," IEEE Symposium on Field-Programmable Custom Computing Machines, April 23--25, 2007, pp. 355--356.
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V. Bonato, E. Marques, and G. A. Constantinides, "A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 18, NO. 12, Dec. 2008.
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L. Yao, H. Feng, Y. Zhu, Z. Jiang, D. Zhao, W. Feng, "An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher," International Conference on Field-Programmable Technology (FPT), Dec. 9--11, 2009, pp.30--37.
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F.-C. Huang, S.-Y. Huang, J.-W. Ker, Y.-C. Chen, "High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction," IEEE Trans. Circuits and Systems for Video Technology, vol.22, no.3, pp.340--351, March 2012.
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Index Terms
- A memory-efficient hardware architecture for real-time feature detection of the SIFT algorithm (abstract only)
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February 2013
294 pages
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Published: 11 February 2013
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FPGA '13
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FPGA '13: The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
February 11 - 13, 2013
California, Monterey, USA
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View all- Liu RTang YFang B(2014)Topological Coding and Its Application in the Refinement of SIFTIEEE Transactions on Cybernetics10.1109/TCYB.2014.230179744:11(2155-2166)Online publication date: Nov-2014
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