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The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing

Authors:

Richard D. Strong,

Jay B. Brockman,

Dean M. Tullsen,

Norman P. JouppiAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 10, Issue 1

Article No.: 5, Pages 1 - 29

https://doi.org/10.1145/2445572.2445577

Published: 01 April 2013 Publication History

Abstract

This article introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At microarchitectural level, McPAT includes models for the fundamental components of a complete chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, and integrated system components such as memory controllers and Ethernet controllers. At circuit level, McPAT supports detailed modeling of critical-path timing, area, and power. At technology level, McPAT models timing, area, and power for the device types forecast in the ITRS roadmap. McPAT has a flexible XML interface to facilitate its use with many performance simulators.

Combined with a performance simulator, McPAT enables architects to accurately quantify the cost of new ideas and assess trade-offs of different architectures using new metrics such as Energy-Delay-Area2 Product (EDA2P) and Energy-Delay-Area Product (EDAP). This article explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting trade-offs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies from cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks for manycore designs at the 22nm technology shows that 8-core clustering gives the best energy-delay product, whereas when die area is taken into account, 4-core clustering gives the best EDA2P and EDAP.

References

[1]

Ahn, H.-T. and Allstot, D. 2000. A low-jitter 1.9-v cmos pll for ultrasparc microprocessor applications. J. Solid State Circ. 35, 3, 450--454.

[2]

AMD. 2002. HyperTransport technology: Simplifying system design. http://www.hypertransport.org/docs/wp/26635A_HT_System_Design.pdf.

[3]

Anis, M., Areibi, S., Mahmoud, M., and Elmasry, M. 2002. Dynamic and leakage power reduction in mtcmos circuits using an automated efficient gate clustering technique. In Proceedings of the 39th Design Automation Conference (DAC). 480--485.

Digital Library

[4]

ARM. 2013. http://www.arm.com/products/processors/cortex-a/cortex-a9.php.

[5]

Auth, C., Buehler, M., Cappellani, A., Hing Choi, C., Ding, G., Han, W., Joshi, S., Mcintyre, B., Prince, M., Ranade, P., Sandford, J., and Thomas, C. 2008. 45nm high-k+metal gate strain-ehanced transistors. Intel Technol. J. 12.

[6]

Bienia, C., Kumar, S., Singh, J. P., and Li, K. 2008. The parsec benchmark suite: Characterization and architectural implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques (PACT).

Digital Library

[7]

Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M. D., and Wood, D. A. 2011. The gem5 simulator. SIGARCH Comput. Archit. News 39, 2.

Digital Library

[8]

Binkert, N. L., Dreslinski, R. G., Hsu, L. R., Lim, K. T., Saidi, A. G., and Reinhardt, S. K. 2006. The m5 simulator: Modeling networked systems. IEEE Micro 26, 4, 52--60.

Digital Library

[9]

Bishop, B., Kelliher, T. P., and Irwin, M. J. 1999. The Design of a register renaming unit. In Proceedings of the 9th Great Lakes Symposium on VLSI.

Digital Library

[10]

Borkar, S., Karnik, T., Narendra, S., Tschanz, J., Keshavarzi, A., and De, V. 2003. Parameter variations and impact on circuits and microarchitecture. In Proceedings of the Design Automation Conference (DAC).

Digital Library

[11]

Broadcom. 2008. BCM57710 - dual-port 10G/2500/1000base-x toe, rdma, isci pci express ether-net controller. http://www.broadcom.com/products/Ethernet-Controllers-and-Adapters/Enterprise-Server-Controllers/BCM57710.

[12]

Brooks, D., Tiwari, V., and Martonosi, M. 2000. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA).

Digital Library

[13]

Brooks, D., Bose, P., Srinivasan, V., Gschwind, M., Emma, P., and Rosenfield, M. 2003. New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. IBM J. Res. Devel. 47.

Digital Library

[14]

Burger, D. and Austin, T. M. 1997. The simplescalar tool set. version 2.0. SIGARCH Comput. Archit. News 25, 3.

Digital Library

[15]

Butler, M. 2010. Bulldozer: A new approach to multithreaded compute performance. In Proceedings of Hot Chips: A Symposium on High Performance Chips.

[16]

Cadence Incyte Chip Estimator. 2013. http://www.chipestimate.com/.

[17]

Cai, G. Z. N. and Lim, C. H. 2012. Microarchitectural power analysis for cpu power/performance optimization. http://web.eecs.umich.edu/~panalyzer/pdfs/Microacrhitectural_Power_Analysis_for_CPU_Power_Performance_Optimization.pdf.

[18]

Elmore, W. C. 1948. The transient response of damped linear netwoks with particular regard to wideband amplifiers. J. Appl. Phys. 19, 55--63.

[19]

Ferdman, M., Lotfi-Kamran, P., Balet, K., and Falsafi, B. 2011. Cuckoo directory: A scalable directory for many-core systems. In Proceedings of the IEEE 17th International Symposium on High Performance Computer Architecture (HPCA). 169--180.

Digital Library

[20]

Fukuda, K., Yamashita, H., Ono, G., Nemoto, R., Suzuki, E., Takemoto, T., Yuki, F., and Saito, T. 2010. A 12.3mW 12.5Gb/s complete transceiver in 65nm cmos. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC’10). 368--369.

[21]

George, V., Jahagirdar, S., Tong, C., Smits, K., Damaraju, S., Siers, S., Naydenov, V., Khond-Ker, T., Sarkar, S., and Singh, P. 2007. Penryn: 45-nm next generation intel core 2 processor. In Proceedings of the IEEE Asian Solid-State Circuits Conference (ASSCC’07).

[22]

Gerard, P. and of Engineering Physics, M. U. D. 1997. Macsim: Simulating the Mcmaster Nuclear Reactor Using a Distributed Approach. McMaster University.

[23]

Gowan, M. K., Biro, L. L., and Jackson, D. B. 1998. Power considerations in the design of the alpha 21264 microprocessor. In Proceedings of the Design Automation Conference (DAC).

Digital Library

[24]

Gunther, S. H., Binns, F., Carmean, M., and Hall, J. C. 2001. Managing the impact of increasing microprocessor power consumption. Intel Technol. J. 1.

[25]

Gupta, S., Keckler, S., and Burger, D. 2000. Technology independent area and delay estimates for microprocessor building blocks. Tech. rep., Department of Computer Science, University of Texas at Austin.

Digital Library

[26]

Harwood, M., Warke, N., Simpson, R., Leslie, T., Amerasekera, A., Batty, S., Colman, D., Carr, E., Gopinathan, V., Hubbins, S., et al. 2007. A 12.5Gb/s SerDes in 65nm cmos using a baud-rate adc with digital receiver equalization and clock recovery. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC’07). 436--591.

[27]

Hennessy, J. L. and Patterson, D. A. 2011. Computer Architecture: A Quantitative Approach 5th Ed. Morgan Kaufmann, San Fransisco, CA.

Digital Library

[28]

Henning, J. L. 2007. Performance counters and development of spec cpu2006. Comput. Archit. News 35, 1.

Digital Library

[29]

Hinton, G., Sager, D., Upton, M., Boggs, D., Group, D. P., and Corp, I. 2001. The microarchitecture of the pentium 4 processor. Intel Technol. J. 1.

[30]

Ho, R. 2003. On-Chip wires: Scaling and efficiency. Ph.D. thesis, Stanford University.

[31]

Horowitz, M. A. 1984. Timing models for mos circuits. Tech. rep., Stanford University.

Digital Library

[32]

Horowitz, M., Ho, R., and Mai, K. 1999. The future of wires. http://velox.stanford.edu/.

[33]

HP. 2009. HP BladeSystem c-class SAN connectivity technology brief. http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00810839/c00810839.pdf.

[34]

Huang, W., Member, S., Ghosh, S., Velusamy, S., Sankaranarayanan, K., Skadron, K., Stan, M. R., Member, S., and Member, S. 2006. Hotspot: A compact thermal modeling method for cmos vlsi systems. IEEE Trans. VLSI 14, 501--513.

Digital Library

[35]

Intel. 1998. P6 family of processors hardware developer’s manual. Intel white paper.

[36]

Intel. 2009. An introduction to the intel quickpath interconnect. http://www.intel.com/content/dam/doc/white-paper/quick-path-interconnect-introduction-paper.pdf.

[37]

Intel. 2013. http://www.intel.com/products/processor/atom/techdocs.htms.

[38]

Jain, A., Anderson, W., Benninghoff, T., Bertucci, D., Braganza, M., Burnette, J., Chang, T., Eble, J., Faber, R., Gowda, D., Grodstein, J., Hess, G., Kowaleski, J., Kumar, A., Miller, B., Mueller, R., Paul, P., Pickholtz, J., Russell, S., Shen, M., Truex, T., Vardharajan, A., Xanthopoulos, D., and Zou, T. 2001. A 1.2 ghz alpha microprocessor with 44.8 GB/s chip pin bandwidth. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC).

[39]

Johnson, T. and Nawathe, U. 2007. An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2). In Proceedings of the International Symposium on Physical Design (ISPD).

Digital Library

[40]

Kahng, A., Li, B., Peh, L.-S., and Samadi, K. 2009. ORION 2.0: A fast and accurate noc power and area model for early-stage design space exploration. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE).

Digital Library

[41]

Kao, J., Narendra, S., and Chandrakasan, A. 1998. MTCMOS hierarchical sizing based on mutual exclusive discharge patterns. In Proceedings of the Design Automation Conference (DAC). 495--500.

Digital Library

[42]

Kessler, R. E. 1999. The alpha 21264 microprocessor. IEEE Micro 19, 2.

Digital Library

[43]

Kongetira, P., Aingaran, K., and Olukotun, K. 2005. Niagara: A 32-way multithreaded sparc processor. IEEE Micro 25, 2.

Digital Library

[44]

Koufaty, D. and Marr, D. T. 2003. Hyperthreading technology in the netburst microarchitecture. IEEE Micro 23, 2.

Digital Library

[45]

Kumar, R. and Hinton, G. 2009. A family of 45nm ia processors. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC). 58--59.

[46]

Kumar, R., Jouppi, N. P., and Tullsen, D. M. 2004. Conjoined-Core chip multiprocessing. In Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 195--206.

Digital Library

[47]

Kumar, R., Zyuban, V., and Tullsen, D. M. 2005. Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA).

Digital Library

[48]

Leon, A. S., Tam, K. W., Shin, J. L., Weisner, D., and Schumacher, F. 2007. A power-efficient high-throughput 32-thread sparc processor. J. Solid State Circ. 42.

[49]

Li, S., Ahn, J. H., Strong, R. D., Brockman, J. B., Tullsen, D. M., and Jouppi, N. P. 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 469--480.

Digital Library

[50]

Li, S., Chen, K., Ahn, J. H., Brockman, J. B., and Jouppi, N. P. 2011. CACTI-P: Architecture-Level modeling for sram-based structures with advanced leakage reduction techniques. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD).

Digital Library

[51]

Long, C. and He, L. 2004. Distributed sleep transistor network for power reduction. IEEE Trans. Very Large Scale Integr. Syst. 12, 937--946.

Digital Library

[52]

Luk, C.-K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V. J., and Hazelwood, K. 2005. Pin: Building customized program analysis tools with dynamic instrumentation. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI).

Digital Library

[53]

Mahoney, P., Fetzer, E., Doyle, B., and Naffziger, S. 2005. Clock distribution on a dual-core multi-threaded itanium family processor. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC).

[54]

Martin, M. M. K., Sorin, D. J., Beckmann, B. M., Marty, M. R., Xu, M., Alameldeen, A. R., Moore, K. E., Hill, M. D., and Wood, D. A. 2005. Multifacet’s general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Comput. Archit. News 33, 4.

Digital Library

[55]

Marty, M. R. and Hill, M. D. 2007. Virtual hierarchies to support server consolidation. SIGARCH Comput. Archit. News 35, 2, 46--56.

Digital Library

[56]

Mathew, S., Anders, M., Bloechel, B., Nguyen, T., Krishnamurthy, R., and Borkar, S. 2005. A 4-GHz 300-mW 64-bit integer execution alu with dual supply voltages in 90-nm cmos. J. Solid State Circ. 40, 1.

[57]

Miller, J. E., Kasture, H., Kurian, G., Iii, C. G., Beckmann, N., Celio, C., Eastep, J., and Agarwal, A. 2010. Graphite: A distributed parallel simulator for multicores. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA). 1--12.

[58]

Naveh, A., Rotem, E., Mendelson, A., Gochman, S., Chabukswar, R., Krishnan, K., and Kumar, A. 2006. Power and thermal management in the intel core duo processor. Intel Technol. J. 10, 109--122.

[59]

Nawathe, U., Hassan, M., Yen, K., Kumar, A., Ramachandran, A., and Greenhill, D. 2008. Implementation of an 8-core, 64-thread, power-efficient sparc server on a chip. J. Solid State Circ. 43, 1.

[60]

Nose, K. and Sakurai, T. 2000. Analysis and future trend of short-circuit power. IEEE Trans. Comput.-Aided Des. 19, 9.

Digital Library

[61]

Palacharla, S., Jouppi, N. P., and Smith, J. E. 1997. Complexity-Effective superscalar processors. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA).

Digital Library

[62]

Palmer, R., Poulton, J., Dally, W., Eyles, J., Fuller, A., Greer, T., Horowitz, M., Kellam, M., Quan, F., and Zarkeshvari, F. 2007. A 14mW 6.25Gb/s transceiver in 90nm cmos for serial chip-to-chip communications. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC’07). 440--614.

[63]

Pan, H., Asanovic, K., Cohn, R., and Luk, C.-K. 2005. Controlling program execution through binary instrumentation. Comput. Archit. News 33, 5.

Digital Library

[64]

Rabaey, J., Chandrakasan, A., and Nikolic, B. 2003. Digital Integrated Circuits: A Design Perspective 2nd Ed. Prentice-Hall, Englewood Cliffs, NJ.

[65]

Ram, K. K., Santos, J. R., Turner, Y., Cox, A. L., and Rixner, S. 2009. Achieving 10 Gb/s using safe and transparent network interface virtualization. In Proceedings of the ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE). 61--70.

Digital Library

[66]

Rodrigues, A. F. 2007. Parametric sizing for processors. Tech. rep., Sandia National Laboratories.

[67]

Rodrigues, A. F., Hemmert, K. S., Barrett, B. W., Kersey, C., Oldfield, R., Weston, M., Risen, R., Cook, J., Rosenfeld, P., Cooperballs, E., and Jacob, B. 2011. The structural simulation toolkit. SIGMETRICS Perform. Eval. Rev. 38, 4.

Digital Library

[68]

Rusu, S., Tam, S., Muljono, H., Ayers, D., and Chang, J. 2006. A dual-core multi-threaded xeon processor with 16mb l3 cache. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC).

[69]

Semiconductor Industries Association. 2007. Model for assessment of cmos technologies and roadmaps (mastar). http://www.itrs.net/models.html.

[70]

Sherwood, T., Perelman, E., Hamerly, G., and Calder, B. 2002. Automatically characterizing large scale program behavior. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).

Digital Library

[71]

Shin, J., Tam, K., Huang, D., Petrick, B., Pham, H., Hwang, C., Li, H., Smith, A., Johnson, T., Schumacher, F., Greenhill, D., Leon, A., and Strong, A. 2010. A 40nm 16-core 128-thread cmt sparc soc processor. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC). 98--99.

[72]

Sima, D. 2000. The design space of register renaming techniques. IEEE Micro 20, 5, 70--83.

Digital Library

[73]

Sun Microsystems. 2013. OpenSPARC. http://www.opensparc.net.

[74]

Thoziyoor, S., Ahn, J., Monchiero, M., Brockman, J., and Jouppi, N. 2008. A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA).

Digital Library

[75]

Tullsen, D. M., Eggers, S. J., Emer, J. S., Levy, H. M., Lo, J. L., and Stamm, R. L. 1996. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA).

Digital Library

[76]

Ubal, R., Sahuquillo, J., Petit, S., and Lpez, P. 2007. Multi2Sim: A simulation framework to evaluate multicore-multithreaded processors. In Proceedings of the International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). 62--68.

[77]

Vangal, S., Borkar, N., and Alvandpour, A. 2005. A six-port 57gb/s double-pumped nonblocking router core. In Proceedings of the Symposium on VLSI Circuits (VLSI).

[78]

Vijaykrishnan, N., Kandemir, M., Irwin, M. J., Kim, H. S., and Ye, W. 2000. Energy-Driven integrated hardware-software optimizations using simplepower. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA).

Digital Library

[79]

Wang, Y., Bhattacharya, U., Hamzaoglu, F., Kolar, P., Ng, Y.-G., Wei, L., Zhang, Y., Zhang, K., and Bohr, M. 2010. A 4.0 ghz 291 mb voltage-scalable sram design in a 32 nm high-k + metal-gate cmos technology with integrated power management. IEEE J. Solid-State Circ. 45, 103--110.

[80]

Wilton, S. and Jouppi, N. P. 1994. An enhanced access and cycle time model for on-chip caches. Tech. rep. 93/5, DEC WRL.

[81]

Woo, S. C., Ohara, M., Torrie, E., Singh, J. P., and Gupta, A. 1995. The splash-2 programs: Characterization and methodological considerations. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA).

Digital Library

[82]

Yoshida, H., De, K., and Boppana, V. 2004. Accurate pre-layout estimation of standard cell characteristics. In Proceedings of the Annual Conference on Design Automation (DAC). ACM Press, NewYork, 208--211.

Digital Library

[83]

Yuffe, M., Knoll, E., Mehalel, M., Shor, J., and Kurts, T. 2011. A fully integrated multi-cpu, gpu and memory controller 32nm processor. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC). 264--266.

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 10, Issue 1

April 2013

151 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2445572

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Published: 01 April 2013

Accepted: 01 November 2012

Revised: 01 November 2012

Received: 01 May 2012

Published in TACO Volume 10, Issue 1

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