research-article

Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems

Authors:

Robert Fischbach,

Johann Knechtel,

Jens LienigAuthors Info & Claims

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

Pages 11 - 16

https://doi.org/10.1145/2451916.2451921

Published: 24 March 2013 Publication History

Abstract

The reuse of predesigned intellectual property (IP) blocks is critical for the commercial success of three-dimensional (3D) electronic circuits. In practice, IP blocks can be specified as rectangular as well as rectilinear 2D blocks. The 3D equivalent of 2D rectilinear blocks, orthogonal polyhedra, may be utilized for modeling tightly interconnected (sub-)modules placed onto adjacent dies or for design automation of versatile 3D-integrated systems. Such complex block geometries have not been adequately considered until now. We propose a new 3D layout representation that enables native 3D floorplanning of complex-shaped 3D blocks, i.e., orthogonal polyhedra spread onto multiple dies. Furthermore, it can also be applied during 3D floorplanning of both rectangular and rectilinear 2D blocks. In the former case, experiments reveal superior estimated wirelength and packing density compared to previous work.

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Cited By

Yu SDu SYang C(2024)A Deep Reinforcement Learning Floorplanning Algorithm Based on Sequence PairsApplied Sciences10.3390/app1407290514:7(2905)Online publication date: 29-Mar-2024
https://doi.org/10.3390/app14072905
Kahng ALienig JMarkov IHu JKahng ALienig JMarkov IHu J(2022)Chip PlanningVLSI Physical Design: From Graph Partitioning to Timing Closure10.1007/978-3-030-96415-3_3(53-93)Online publication date: 15-Jun-2022
https://doi.org/10.1007/978-3-030-96415-3_3
Roy PDutt ARahaman H(2020)3-D IC: An Overview of Technologies, Design Methodology, and Test StrategiesProceedings of International Conference on Frontiers in Computing and Systems10.1007/978-981-15-7834-2_81(859-871)Online publication date: 24-Nov-2020
https://doi.org/10.1007/978-981-15-7834-2_81
Show More Cited By

Index Terms

Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning

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cover image ACM Conferences

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

March 2013

194 pages

ISBN:9781450319546

DOI:10.1145/2451916

General Chair:
Cheng-Kok Koh
Purdue University
,
Program Chair:
Cliff Sze
IBM Research

Copyright © 2013 ACM.

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SIGDA: ACM Special Interest Group on Design Automation

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Published: 24 March 2013

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ISPD'13: International Symposium on Physical Design

March 24 - 27, 2013

Nevada, Stateline, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Yu SDu SYang C(2024)A Deep Reinforcement Learning Floorplanning Algorithm Based on Sequence PairsApplied Sciences10.3390/app1407290514:7(2905)Online publication date: 29-Mar-2024
https://doi.org/10.3390/app14072905
Kahng ALienig JMarkov IHu JKahng ALienig JMarkov IHu J(2022)Chip PlanningVLSI Physical Design: From Graph Partitioning to Timing Closure10.1007/978-3-030-96415-3_3(53-93)Online publication date: 15-Jun-2022
https://doi.org/10.1007/978-3-030-96415-3_3
Roy PDutt ARahaman H(2020)3-D IC: An Overview of Technologies, Design Methodology, and Test StrategiesProceedings of International Conference on Frontiers in Computing and Systems10.1007/978-981-15-7834-2_81(859-871)Online publication date: 24-Nov-2020
https://doi.org/10.1007/978-981-15-7834-2_81
HAO CYOSHIMURA T(2017)An Efficient Multi-Level Algorithm for 3D-IC TSV AssignmentIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E100.A.776E100.A:3(776-784)Online publication date: 2017
https://doi.org/10.1587/transfun.E100.A.776

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