research-article

Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data

Authors:

Wangyang Zhang,

Chenjie GuAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 64, Pages 1 - 6

https://doi.org/10.1145/2463209.2488812

Published: 29 May 2013 Publication History

Abstract

Efficient high-dimensional performance modeling of today's complex analog and mixed-signal (AMS) circuits with large-scale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our key idea is to borrow the simulation data generated from an early stage (e.g., schematic level) to facilitate efficient high-dimensional performance modeling at a late stage (e.g., post layout) with low computational cost. Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Several circuit examples designed in a commercial 32nm CMOS process demonstrate that BMF achieves up to 9x runtime speedup over the traditional modeling technique without surrendering any accuracy.

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Lu TZhai XChen SLiu YWan JLiu GLi X(2024)Robust battery lifetime prediction with noisy measurements via total-least-squares regressionIntegration, the VLSI Journal10.1016/j.vlsi.2023.10213696:COnline publication date: 1-May-2024
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Gao XZhang HYe SLiu MPan DShen LWang RLin YHuang R(2024)Post-layout simulation driven analog circuit sizingScience China Information Sciences10.1007/s11432-022-3878-567:4Online publication date: 20-Mar-2024
https://doi.org/10.1007/s11432-022-3878-5
Beaulieu PDumesnil ÉNabki FBoukadoum M(2023)Analog RF Circuit Sizing by a Cascade of Shallow Neural NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328257042:12(4391-4401)Online publication date: 1-Dec-2023
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Index Terms

Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Hardware validation

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

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Cited By

Lu TZhai XChen SLiu YWan JLiu GLi X(2024)Robust battery lifetime prediction with noisy measurements via total-least-squares regressionIntegration, the VLSI Journal10.1016/j.vlsi.2023.10213696:COnline publication date: 1-May-2024
https://dl.acm.org/doi/10.1016/j.vlsi.2023.102136
Gao XZhang HYe SLiu MPan DShen LWang RLin YHuang R(2024)Post-layout simulation driven analog circuit sizingScience China Information Sciences10.1007/s11432-022-3878-567:4Online publication date: 20-Mar-2024
https://doi.org/10.1007/s11432-022-3878-5
Beaulieu PDumesnil ÉNabki FBoukadoum M(2023)Analog RF Circuit Sizing by a Cascade of Shallow Neural NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328257042:12(4391-4401)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3282570
Mohan AK A(2023)AMS circuit modeling by Bayesian Model Fusion2023 International Conference on Control, Communication and Computing (ICCC)10.1109/ICCC57789.2023.10165321(1-5)Online publication date: 19-May-2023
https://doi.org/10.1109/ICCC57789.2023.10165321
Fayazi MTaba MTabatabavakili AAfshari EDreslinski R(2023)FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323890(1-8)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323890
Chatterjee STiru B(2023)Design and testing of a bit error rate tester with application to a visible light communication systemMaterials Today: Proceedings10.1016/j.matpr.2023.03.786Online publication date: Apr-2023
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Pietrenko-Dabrowska AKoziel SPietrenko-Dabrowska AKoziel S(2023)IntroductionResponse Feature Technology for High-Frequency Electronics. Optimization, Modeling, and Design Automation10.1007/978-3-031-43845-5_1(1-24)Online publication date: 17-Oct-2023
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Koziel SCalik NMahouti PBelen M(2022)Accurate Modeling of Antenna Structures by Means of Domain Confinement and Pyramidal Deep Neural NetworksIEEE Transactions on Antennas and Propagation10.1109/TAP.2021.311129970:3(2174-2188)Online publication date: Mar-2022
https://doi.org/10.1109/TAP.2021.3111299
Wang ZHu WZhou JZhang WWang RZhang JDou DYe ZWang Y(2022)Building Post-layout Performance Model of Analog/RF Circuits by Fine-tuning Technique2022 23rd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED54688.2022.9806251(1-6)Online publication date: 6-Apr-2022
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Lai WJian RXiaoning X(2020)Noise Suppression of Artificial Intelligence Filter for Radio Frequency Interference2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan)10.1109/ICCE-Taiwan49838.2020.9258177(1-2)Online publication date: 28-Sep-2020
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