research-article

Power benefit study for ultra-high density transistor-level monolithic 3D ICs

Authors:

Young-Joon Lee,

Daniel Limbrick,

Sung Kyu LimAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 104, Pages 1 - 10

https://doi.org/10.1145/2463209.2488863

Published: 29 May 2013 Publication History

Get Access

Abstract

The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high density device integration at the individual transistor-level. In this paper we demonstrate the power benefits of transistor-level monolithic 3D designs. We first build a cell library that consists of 3D gates and model their timing/power characteristics. Next, we build timing-closed, full-chip GDSII layouts and perform sign-off iso-performance power comparisons with 2D IC designs. We also study the characteristics of benchmark circuits that maximize the power benefits in monolithic 3D designs. Lastly, our study is extended to predict the power benefits of monolithic 3D designs built with future devices.

References

[1]

P. Batude et al. Advances in 3D CMOS Sequential Integration. In Proc. IEEE Int. Electron Devices Meeting, pages 1--4, 2009.

Crossref

Google Scholar

[2]

S. Bobba et al. CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits. In Proc. Asia and South Pacific Design Automation Conf., pages 336--343, 2011.

Digital Library

Google Scholar

[3]

K. D. Boese, A. B. Kahng, and S. Mantik. On the Relevance of Wire Load Models. In Proc. Int. Workshop on System-Level Interconnect Prediction, pages 91--98, 2001.

Digital Library

Google Scholar

[4]

N. Golshani et al. Monolithic 3D Integration of SRAM and Image Sensor Using Two Layers of Single Grain Silicon. In Proc. IEEE Int. Conf. on 3D System Integration, pages 1--4, 2010.

Google Scholar

[5]

International Technology Roadmap for Semiconductors. ITRS 2011 Edition.

Google Scholar

[6]

S.-M. Jung et al. The Revolutionary and Truly 3-Dimensional 25F² SRAM Technology with the smallest S³ (Stacked Single-crystal Si) Cell, 0.16um², and SSTFT (Stacked Single-crystal Thin Film Transistor) for Ultra High Density SRAM. In Proc. Symposium on VLSI Technology, pages 228--229, 2004.

Google Scholar

[7]

Y.-J. Lee, P. Morrow, and S. K. Lim. Ultra High Density Logic Designs Using Transistor-Level Monolithic 3D Integration. In Proc. IEEE Int. Conf. on Computer-Aided Design, pages 539--546, 2012.

Digital Library

Google Scholar

[8]

C. Liu and S. K. Lim. A Design Tradeoff Study with Monolithic 3D Integration. In Proc. Int. Symp. on Quality Electronic Design, pages 531--538, 2012.

Crossref

Google Scholar

[9]

T. Naito et al. World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS. In Proc. Symposium on VLSI Technology, pages 219--220, 2010.

Google Scholar

[10]

Nangate. Nangate 45nm Open Cell Library.

Google Scholar

[11]

S. Sinha et al. Exploring Sub-20nm FinFET Design with Predictive Technology Models. In Proc. ACM Design Automation Conf., pages 283--288, 2012.

Digital Library

Google Scholar

Cited By

View all

Mansoor AChrzanowska-Jeske MJeske M(2024)AI-Enabled Placement for 2D and 3D ICsAI-Enabled Electronic Circuit and System Design10.1007/978-3-031-71436-8_6(189-223)Online publication date: 17-Oct-2024
https://doi.org/10.1007/978-3-031-71436-8_6
Ge MNi XChen SKang Y(2022)Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.310734069:3(1552-1556)Online publication date: Mar-2022
https://doi.org/10.1109/TCSII.2021.3107340
Mansoor AChrzanowska-Jeske M(2022)RS3DPlace: Monolithic 3D IC placement using Reinforcement Learning and Simulated Annealing2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937281(394-398)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937281
Show More Cited By

Index Terms

Power benefit study for ultra-high density transistor-level monolithic 3D ICs
1. Hardware
  1. Hardware validation

Recommendations

Design and CAD methodologies for low power gate-level monolithic 3D ICs
ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-...
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs
ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design

In this paper, we develop physical design tools and methodologies to tackle the inter-tier performance variations caused by low temperature manufacturing in 2-tier gate-level monolithic 3D ICs (M3D). First, we model the top tier front-end-of-line (FEOL) ...
Ultra high density logic designs using transistor-level monolithic 3D integration
ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

Recent innovations in monolithic 3D technology enable much higher-density vertical connections than today's through-silicon-via (TSV)-based technology. In this paper, we investigate the benefits and challenges of monolithic 3D integration technology for ...

Comments

Information & Contributors

Information

Published In

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DAC '13

Sponsor:

EDAC
SIGDA

DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

52
Total Citations
View Citations
481
Total Downloads

Downloads (Last 12 months)18
Downloads (Last 6 weeks)1

Reflects downloads up to 10 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Mansoor AChrzanowska-Jeske MJeske M(2024)AI-Enabled Placement for 2D and 3D ICsAI-Enabled Electronic Circuit and System Design10.1007/978-3-031-71436-8_6(189-223)Online publication date: 17-Oct-2024
https://doi.org/10.1007/978-3-031-71436-8_6
Ge MNi XChen SKang Y(2022)Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.310734069:3(1552-1556)Online publication date: Mar-2022
https://doi.org/10.1109/TCSII.2021.3107340
Mansoor AChrzanowska-Jeske M(2022)RS3DPlace: Monolithic 3D IC placement using Reinforcement Learning and Simulated Annealing2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937281(394-398)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937281
Yu WMascagni MYu WMascagni M(2022)FRW Based Techniques for Handling Cylindrical Inter-Tier-ViasMonte Carlo Methods for Partial Differential Equations With Applications to Electronic Design Automation10.1007/978-981-19-3250-2_6(87-120)Online publication date: 3-Sep-2022
https://doi.org/10.1007/978-981-19-3250-2_6
Bamberg LJoseph JGarcía-Ortiz APionteck TBamberg LJoseph JGarcía-Ortiz APionteck T(2022)Introduction to 3D Technologies3D Interconnect Architectures for Heterogeneous Technologies10.1007/978-3-030-98229-4_1(3-25)Online publication date: 12-Mar-2022
https://doi.org/10.1007/978-3-030-98229-4_1
Tamir ASalem MLin JAlasad QYuan J(2021)Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R ToolElectronics10.3390/electronics1016193010:16(1930)Online publication date: 11-Aug-2021
https://doi.org/10.3390/electronics10161930
Dhananjay KShukla PPavlidis VCoskun ASalman E(2021)Monolithic 3D Integrated Circuits: Recent Trends and Future ProspectsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.3051250(1-1)Online publication date: 2021
https://doi.org/10.1109/TCSII.2021.3051250
Wang RChang YXie Y(2020)Routability-aware pin access optimization for monolithic 3D designsProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415719(1-6)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415719
Zanelli JMetzler CReis R(2020)Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS45839.2020.9069042(1-4)Online publication date: Feb-2020
https://doi.org/10.1109/LASCAS45839.2020.9069042
Kim SJeong YBidenko PLim HJeon YKim HLee YGeum DHan JChoi CKim HKim S(2020)3D Stackable Synaptic Transistor for 3D Integrated Artificial Neural NetworksACS Applied Materials & Interfaces10.1021/acsami.9b2200812:6(7372-7380)Online publication date: 15-Jan-2020
https://doi.org/10.1021/acsami.9b22008
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Design and CAD methodologies for low power gate-level monolithic 3D ICs

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs

Ultra high density logic designs using transistor-level monolithic 3D integration

Comments

Information

Published In

Sponsors

In-Cooperation

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations