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Allocating rotating registers by scheduling

Published: 07 December 2013 Publication History
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  • Abstract

    A rotating alias register file is a scalable hardware support to detect memory aliases at run-time. It has been shown that it can enable instruction-level parallelism to be effectively exploited from sequential code. Yet it is unknown how to apply it to loops.
    This paper presents an elegant and efficient solution that allocates rotating alias registers for a software-pipelined schedule of a loop. We show that surprisingly, this specific register allocation problem can be reduced to another software pipelining problem, for which numerous efficient algorithms are available. This is interesting in both theory and practice. We propose an algorithmic framework to solve the problem. We also present a simple software pipelining algorithm that specially targets register allocation. Comparison with a few other algorithms shows that it usually achieves the best allocation at the least time cost.
    Finally, we generalize the approach to allocate general-purpose (integer/floating-point/predicate) rotating registers by showing that it is also a software pipelining problem.

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    Cited By

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    • (2015)Enabling Efficient Alias SpeculationACM SIGPLAN Notices10.1145/2808704.275496450:5(1-10)Online publication date: 4-Jun-2015
    • (2015)Enabling Efficient Alias SpeculationProceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM10.1145/2670529.2754964(1-10)Online publication date: 4-Jun-2015
    • (2014)Just-In-Time Software PipeliningProceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization10.1145/2581122.2544148(11-22)Online publication date: 15-Feb-2014
    • Show More Cited By

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      cover image ACM Conferences
      MICRO-46: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
      December 2013
      498 pages
      ISBN:9781450326384
      DOI:10.1145/2540708
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 07 December 2013

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      Author Tags

      1. alias
      2. register allocation
      3. scheduling
      4. software pipelining

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      View all
      • (2015)Enabling Efficient Alias SpeculationACM SIGPLAN Notices10.1145/2808704.275496450:5(1-10)Online publication date: 4-Jun-2015
      • (2015)Enabling Efficient Alias SpeculationProceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM10.1145/2670529.2754964(1-10)Online publication date: 4-Jun-2015
      • (2014)Just-In-Time Software PipeliningProceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization10.1145/2581122.2544148(11-22)Online publication date: 15-Feb-2014
      • (2014)Just-In-Time Software PipeliningProceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization10.1145/2544137.2544148(11-22)Online publication date: 15-Feb-2014

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