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Built-in generation of functional broadside tests considering primary input constraints

Published: 20 May 2014 Publication History

Abstract

This paper describes a method for built-in generation of functional broadside tests for a circuit that is embedded in a larger design, taking functional constraints on its primary input sequences into account. The constraints are captured by functional input sequences of the design. Specifically, the peak switching activity in the circuit under the functional input sequences is used to bound the switching activity during on-chip test generation.

References

[1]
I. Pomeranz, "Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure," IEEE TVLSI Syst., Jan. 2013, pp. 124--132.
[2]
I. Pomeranz and S. M. Reddy, "Generation of functional broadside tests for transition faults," IEEE TCAD Integr. Circuits Syst., Oct. 2006, pp. 2207--2218.
[3]
I. Pomeranz and S. M. Reddy, "Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits," IEEE TCAD, Jan. 2008, pp.193--197.
[4]
I. Pomeranz, "Generation of Functional Broadside Tests for Logic Blocks with Constrained Primary Input Sequences," IEEE TCAD Integr. Circuits Syst., Mar. 2013, pp. 442--452.

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  1. Built-in generation of functional broadside tests considering primary input constraints

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    cover image ACM Conferences
    GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI
    May 2014
    376 pages
    ISBN:9781450328166
    DOI:10.1145/2591513
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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    Published: 20 May 2014

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    Author Tags

    1. built-in test generation
    2. functional broadside tests
    3. primary input constraints
    4. transition faults

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    GLSVLSI '14: Great Lakes Symposium on VLSI 2014
    May 21 - 23, 2014
    Texas, Houston, USA

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    GLSVLSI '14 Paper Acceptance Rate 49 of 179 submissions, 27%;
    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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