research-article

TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis

Authors:

Mahmoud Elbayoumi,

Mihir Choudhury,

Victor Kravets,

Andrew Sullivan,

Mustafa ElnainayAuthors Info & Claims

DAC '14: Proceedings of the 51st Annual Design Automation Conference

Pages 1 - 6

https://doi.org/10.1145/2593069.2593227

Published: 01 June 2014 Publication History

Abstract

Achieving timing-closure has become one of the hardest tasks in logic synthesis due to the required stringent timing constraints in very large circuit designs. In this paper, we propose a novel synthesis paradigm to achieve timing-closure called Timing-Aware CUt Enumeration (TACUE). In TACUE, optimization is conducted through three aspects: (1) a new divide-and-conquer strategy is proposed that generates multiple sub-cuts on the critical parts of the circuit; (2) two cut enumeration strategies are proposed; (3) an efficient parallel synthesis framework is offered to reduce computation time. Experiments on large and difficult industrial benchmarks show the promise of the proposed method.

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Cited By

Li LLi RHa Y(2023)A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325174142:11(3972-3984)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3251741
Amarú LSoeken MVuillod PLuo JMishchenko AGaillardon POlson JBrayton RDe Micheli GParameswaran S(2017)Enabling exact delay synthesisProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199747(352-359)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199747
Amaru LSoeken MVuillod PLuo JMishchenko AGaillardon POlson JBrayton RDe Micheli G(2017)Enabling exact delay synthesis2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203799(352-359)Online publication date: Nov-2017
https://doi.org/10.1109/ICCAD.2017.8203799
Show More Cited By

Index Terms

TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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cover image ACM Other conferences

DAC '14: Proceedings of the 51st Annual Design Automation Conference

June 2014

1249 pages

ISBN:9781450327305

DOI:10.1145/2593069

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGBED: ACM Special Interest Group on Embedded Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2014

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DAC '14

DAC '14: The 51st Annual Design Automation Conference 2014

June 1 - 5, 2014

CA, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Li LLi RHa Y(2023)A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325174142:11(3972-3984)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3251741
Amarú LSoeken MVuillod PLuo JMishchenko AGaillardon POlson JBrayton RDe Micheli GParameswaran S(2017)Enabling exact delay synthesisProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199747(352-359)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199747
Amaru LSoeken MVuillod PLuo JMishchenko AGaillardon POlson JBrayton RDe Micheli G(2017)Enabling exact delay synthesis2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203799(352-359)Online publication date: Nov-2017
https://doi.org/10.1109/ICCAD.2017.8203799
Elbayoumi MHsiao MElNainay M(2015)Novel SAT-based invariant-directed low-power synthesisSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085428(217-222)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085428
Puri RChoudhury MQian HZiegler MXie YKarnik TKhellah MMehra R(2014)Bridging high performance and low power in processor designProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2631642(183-188)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2631642

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