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View all- Walter DTeich JArun-Kumar SMery DSaha IZhang L(2021)LIONProceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design10.1145/3487212.3487349(32-43)Online publication date: 20-Nov-2021
Emulations of cellular nonlinear networks (CNN) on digital reconfigurable hardware have proved to be adequate for highly-efficient computation of massive data, exceeding the accuracy and flexibility of full-custom designs. Based on a recently-proposed ...
This paper presents an adaptive heap sort architecture for an image coding implementation on FPGA, which specifically addresses the issue of sorting different amount of data located in each subband during the coding. The proposed sorting architecture is ...
This paper describes the implementation of a reconfigurable hardware-based genetic algorithm (HGA) accelerator using the hardware-software (HW/SW) co-design methodology. This HGA is coupled with a unique TRNG that extracts random jitters from a phase ...
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