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Robust IP watermarking methodologies for physical design

Authors:

Gregory WolfeAuthors Info & Claims

DAC '98: Proceedings of the 35th annual Design Automation Conference

Pages 782 - 787

https://doi.org/10.1145/277044.277241

Published: 01 May 1998 Publication History

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Abstract

Increasingly popular reuse-based design paradigms create a pressing need for authorship enforcement techniques that protect the intellectual property rights of designers. We develop the first intellectual property protection protocols for embedding design watermarks at the physical design level. We demonstrate that these protocols are tarnsparent with respect to existing industrial tools and design flows, and that they can embed watermarks into real-world industrial designs with very low implementation overhead (as measured by such standard metrics as wirelength, layout area, number of vias, routing congestion and CPU time). On several industrial test cases, we obtain extremely strong, tamper-resistant proofs of authorship for placement and routing solutions.

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Cited By

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Gandhi JShekhawat DSantosh MPandey J(2023)Logic locking for IP securityComputers and Security10.1016/j.cose.2023.103196129:COnline publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1016/j.cose.2023.103196
Biswas A(2022)Using Pattern of On-Off Routers and Links and Router Delays to Protect Network-on-Chip Intellectual PropertyACM Transactions on Computer Systems10.1145/354868040:1-4(1-19)Online publication date: 24-Nov-2022
https://dl.acm.org/doi/10.1145/3548680
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https://dl.acm.org/doi/10.1145/3504034
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Robust IP watermarking methodologies for physical design

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Published In

DAC '98: Proceedings of the 35th annual Design Automation Conference

May 1998

820 pages

ISBN:0897919645

DOI:10.1145/277044

Chairmen:
Basant R. Chawla
Lucent Technologies, Warren, NJ
,
Randal E. Bryant
Carnegie Mellon Univ., Pittsburgh, PA
,
Jan M. Rabaey
Univ. of California, Berkeley
,
Editor:
M. J. Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1998

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DAC98

Sponsor:

EDAC
SIGDA
IEEE-CS

DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference

June 15 - 19, 1998

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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June 22 - 26, 2025

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Cited By

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Gandhi JShekhawat DSantosh MPandey J(2023)Logic locking for IP securityComputers and Security10.1016/j.cose.2023.103196129:COnline publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1016/j.cose.2023.103196
Biswas A(2022)Using Pattern of On-Off Routers and Links and Router Delays to Protect Network-on-Chip Intellectual PropertyACM Transactions on Computer Systems10.1145/354868040:1-4(1-19)Online publication date: 24-Nov-2022
https://dl.acm.org/doi/10.1145/3548680
Hong ZYue C(2022)Efficient-Grad: Efficient Training Deep Convolutional Neural Networks on Edge Devices with Gradient OptimizationsACM Transactions on Embedded Computing Systems10.1145/350403421:2(1-24)Online publication date: 8-Feb-2022
https://dl.acm.org/doi/10.1145/3504034
Biswas ASikdar B(2022)Protecting Network-on-Chip Intellectual Property Using Timing Channel FingerprintingACM Transactions on Embedded Computing Systems10.1145/349556521:2(1-21)Online publication date: 8-Feb-2022
https://dl.acm.org/doi/10.1145/3495565
Dong JZheng FLin JLiu ZXiao FFan G(2022)EC-ECC: Accelerating Elliptic Curve Cryptography for Edge Computing on Embedded GPU TX2ACM Transactions on Embedded Computing Systems10.1145/349273421:2(1-25)Online publication date: 8-Feb-2022
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Chen XOgras UChakrabarti C(2022)Probabilistic Risk-Aware Scheduling with Deadline Constraint for Heterogeneous SoCsACM Transactions on Embedded Computing Systems10.1145/348940921:2(1-27)Online publication date: 8-Feb-2022
https://dl.acm.org/doi/10.1145/3489409
Pilato CSciuto DRegazzoni FGarg SKarri R(2021)Protecting Hardware IP Cores During High-Level SynthesisBehavioral Synthesis for Hardware Security10.1007/978-3-030-78841-4_6(95-115)Online publication date: 28-May-2021
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Biswas A(2020)Network-on-Chip Intellectual Property Protection Using Circular Path--based FingerprintingACM Journal on Emerging Technologies in Computing Systems10.1145/341002417:1(1-22)Online publication date: 17-Sep-2020
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Duvalsaint DJin XNiewenhuis BBlanton R(2019)Characterization of Locked Combinational Circuits via ATPG2019 IEEE International Test Conference (ITC)10.1109/ITC44170.2019.9000130(1-10)Online publication date: Nov-2019
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Watermarking techniques for intellectual property protection

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