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rIOMMU: Efficient IOMMU for I/O Devices that Employ Ring Buffers

Published: 14 March 2015 Publication History
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  • Abstract

    The IOMMU allows the OS to encapsulate I/O devices in their own virtual memory spaces, thus restricting their DMAs to specific memory pages. The OS uses the IOMMU to protect itself against buggy drivers and malicious/errant devices. But the added protection comes at a cost, degrading the throughput of I/O-intensive workloads by up to an order of magnitude. This cost has motivated system designers to trade off some safety for performance, e.g., by leaving stale information in the IOTLB for a while so as to amortize costly invalidations. We observe that high-bandwidth devices---like network and PCIe SSD controllers---interact with the OS via circular ring buffers that induce a sequential, predictable workload. We design a ring IOMMU (rIOMMU) that leverages this characteristic by replacing the virtual memory page table hierarchy with a circular, flat table. A flat table is adequately supported by exactly one IOTLB entry, making every new translation an implicit invalidation of the former and thus requiring explicit invalidations only at the end of I/O bursts. Using standard networking benchmarks, we show that rIOMMU provides up to 7.56x higher throughput relative to the baseline IOMMU, and that it is within 0.77--1.00x the throughput of a system without IOMMU protection.

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    Published In

    cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 50, Issue 4
    ASPLOS '15
    April 2015
    676 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/2775054
    • Editor:
    • Andy Gill
    Issue’s Table of Contents
    • cover image ACM Conferences
      ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems
      March 2015
      720 pages
      ISBN:9781450328357
      DOI:10.1145/2694344
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 14 March 2015
    Published in SIGPLAN Volume 50, Issue 4

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    1. I/O memory management unit

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    • (2023)CLMalloc: contiguous memory management mechanism for large-scale CPU-accelerator hybrid architecturesThird International Symposium on Computer Engineering and Intelligent Communications (ISCEIC 2022)10.1117/12.2660807(31)Online publication date: 2-Feb-2023
    • (2021)Characterizing, exploiting, and detecting DMA code injection vulnerabilities in the presence of an IOMMUProceedings of the Sixteenth European Conference on Computer Systems10.1145/3447786.3456249(395-409)Online publication date: 21-Apr-2021
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