research-article

Smart Reconfiguration Approach for Fault-Tolerant NoC Based MPSoCs

Authors:

Jarbas Silveira,

Ramon FernandesAuthors Info & Claims

SBCCI '15: Proceedings of the 28th Symposium on Integrated Circuits and Systems Design

Article No.: 27, Pages 1 - 6

https://doi.org/10.1145/2800986.2801027

Published: 31 August 2015 Publication History

Abstract

Newest technologies of integrated circuits fabrication allow billions of transistors arranged in a single chip enabling to implement a complex parallel system, which requires a high scalable and parallel communication architecture, such as a Network-on-Chip (NoC). These technologies are very close to physical limitations increasing faults in manufacture and at runtime. Thus, it is essential to provide a fault recovery mechanism for NoC operation in the presence of faults. The preprocessing of the most probable fault scenarios and flits retransmission capability enable to anticipate the calculation of deadlock-free routings, reducing the time necessary to interrupt the system in a fault occurrence and maintaining links operating with retransmission capability. This work proposes a smart decisions mechanism for errors on NoC links, which is composed of a hardware part implemented into the links and routers, and a software part implemented inside an operating system kernel of each processor. The mechanism defines thresholds where is better to reconfigure the NoC or to retransmit flits with errors. Experimental results, with several NoC sizes and some error models, suggest when is better to reconfigure the NoC and when is better to maintain some links operating with eventual faults.

References

[1]

International Technology Roadmap for Semiconductors (ITRS). ITRS 2013 Edition. Available in: www.itrs.net/reports.html.

[2]

R. Marculescu et al. Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives. TCAD, v.28, n.1, pp.3--21, Jan. 2009.

Digital Library

[3]

S. Rodrigo et al. Cost Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. TCAD, v.30, n.4, pp.534--547, Apr. 2011.

Digital Library

[4]

E. Ioannidis et al. Evolution of Low Frequency Noise and Noise Variability through CMOS Bulk Technology Nodes from 0.5 μm down to 20 nm. Solid-State Electronics, v.95, pp.28--31, May 2014.

[5]

A. Mejia et al. Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Transactions on VLSI Systems, v.17, n.3, pp.356--369, Mar. 2009.

Digital Library

[6]

K. Aisopos et al. ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment. PACT, pp.298--309, Oct. 2011.

Digital Library

[7]

A. DeOrio et al. A Reliable Routing Architecture and Algorithm for NoCs. TCAD, v.31, n.5, May 2012.

Digital Library

[8]

C. Marcon et al. Phoenix NoC: A distributed fault tolerant architecture. ICCD, pp.7--12, 2013.

[9]

C. Feng et al. Addressing Transient and Permanent Faults in NoC with Efficient Fault-Tolerant Deflection Router. IEEE Transactions on VLSI Systems, v.21, n.6, pp.1053--1066, Jun. 2013.

Digital Library

[10]

Z. Ying et al. Fault-tolerant schemes for NoC with a network monitor. ISCIT, pp.1083--1086, 2010.

[11]

Q. Yu, P. Ampadu, A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links. IEEE Transactions on Circuits and Systems II: Express Briefs, v.58, n.1, pp.36--40, Jan. 2011

[12]

M. Radetzki et al. Methods for fault tolerance in networks-on-chip. ACM Computing Surveys. v.46, n.1, pp.8:1--8:38, 2013.

Digital Library

[13]

M. Palesi, S. Kumar, R. Holsmark. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS, pp.373--384, 2006.

Digital Library

[14]

E. Bolotin et al. Routing Table Minimization for Irregular Mesh NoCs. Design, DATE, pp, 16--20, 2007.

Digital Library

[15]

Y. Fukushima, M. Fukushi, I. Yairi, A Region-Based Fault-Tolerant Routing Algorithm for 2D Irregular Mesh Network-on-Chip, Journal of Electronic Testing, v.29, n.3, pp.415--429, May 2013.

Digital Library

[16]

R. Holsmark, M. Palesi, S. Kumar. Deadlock-Free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions. JSA, v.54, n.3-4, pp.427--440, Mar.-Apr. 2008.

Digital Library

[17]

D. Fick et al. Vicis: A Reliable Network for Unreliable Silicon. DAC, pp.812--817, 2009.

Digital Library

[18]

F. Triviño et al. Network-on-Chip Virtualization in Chip-Multiprocessor Systems. JSA, v.58, n.3--4, pp.126--139, Mar. 2012.

Digital Library

[19]

L. Dai et al. Monitoring Circuit Based on Threshold for Fault-tolerant NoC. Electronics Letters, v.46, n.14, pp.984--985, 2010.

[20]

J. Silveira et al. Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs. PDP, pp.404--411, 2015.

Digital Library

[21]

M. Shintani et al. A Variability-Aware Adaptive Test Flow for Test Quality Improvement. TCAD, v.33, n.7, pp.1056--1066, Jul. 2014.

[22]

B. Hargreaves, H. Hult, S. Reda. Within-die Process Variations: How accurately can they be statistically modeled? ASP-DAC, pp.524--530, 2008.

Digital Library

[23]

International Technology Roadmap for Semiconductors (ITRS). ITRS 2007 Edition. Available in: www.itrs.net/reports.html.

[24]

J. Silveira et al. A fault prediction module for a fault tolerant NoC operation. ISQED, pp.284--288, 2015.

Cited By

Bhanu PJ. S(2021)Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-ChipJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102026116:COnline publication date: 1-Jun-2021
https://dl.acm.org/doi/10.1016/j.sysarc.2021.102026
Fernandes RMarcon CCataldo RSepúlveda J(2020)Using Smart Routing for Secure and Dependable NoC-Based MPSoCsIEEE/ACM Transactions on Networking10.1109/TNET.2020.297937228:3(1158-1171)Online publication date: 16-Jun-2020
https://dl.acm.org/doi/10.1109/TNET.2020.2979372
Milfont RMota RFerreira JCortez PMarcon CTavares DSilveira JSilveira J(2017)Latency reduction of fault-tolerant NoCs by employing multiple pathsProceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands10.1145/3109984.3109985(72-78)Online publication date: 28-Aug-2017
https://dl.acm.org/doi/10.1145/3109984.3109985

Index Terms

Smart Reconfiguration Approach for Fault-Tolerant NoC Based MPSoCs
1. Hardware
  1. Hardware test
  2. Robustness

Recommendations

Scenario preprocessing approach for the reconfiguration of fault-tolerant NoC-based MPSoCs

The latest technologies of integrated circuit manufacturing allow billions of transistors to be arranged on a single chip, enabling the chip to implement a complex parallel system, which requires a communications architecture that has high scalability ...
Hierarchical multi-agent protection system for NoC based MPSoCs
S&D4RCES '10: Proceedings of the International Workshop on Security and Dependability for Resource Constrained Embedded Systems

Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of ...
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults
MICRO-46: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

As silicon continues to scale, transistor reliability is becoming a major concern. At the same time, increasing transistor counts are causing a rapid shift towards large chip multi-processors (CMP) and system-on-chip (SoC) designs, comprising several ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

SBCCI '15: Proceedings of the 28th Symposium on Integrated Circuits and Systems Design

August 2015

279 pages

ISBN:9781450337632

DOI:10.1145/2800986

General Chair:
Robson Nunes de Lima
UFBA, Brazil
,
Program Chairs:
Ana Isabela Araújo Cunha
UFBA, Brazil
,
Calvin Plett
Carleton University, Canada
,
Publications Chair:
Wagner Luiz Alves de Oliveira
UFBA, Brazil

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SBC: Brazilian Computer Society
SIGDA: ACM Special Interest Group on Design Automation
SBMICRO: Brazilian Microelectronics Society

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 August 2015

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

SBCCI '15

Sponsor:

SBC
SIGDA
SBMICRO

SBCCI '15: 28th Symposium on Integrated Circuits and Systems Design

August 31 - September 4, 2015

Salvador, Brazil

Acceptance Rates

SBCCI '15 Paper Acceptance Rate 43 of 98 submissions, 44%;

Overall Acceptance Rate 133 of 347 submissions, 38%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
131
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 17 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Bhanu PJ. S(2021)Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-ChipJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102026116:COnline publication date: 1-Jun-2021
https://dl.acm.org/doi/10.1016/j.sysarc.2021.102026
Fernandes RMarcon CCataldo RSepúlveda J(2020)Using Smart Routing for Secure and Dependable NoC-Based MPSoCsIEEE/ACM Transactions on Networking10.1109/TNET.2020.297937228:3(1158-1171)Online publication date: 16-Jun-2020
https://dl.acm.org/doi/10.1109/TNET.2020.2979372
Milfont RMota RFerreira JCortez PMarcon CTavares DSilveira JSilveira J(2017)Latency reduction of fault-tolerant NoCs by employing multiple pathsProceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands10.1145/3109984.3109985(72-78)Online publication date: 28-Aug-2017
https://dl.acm.org/doi/10.1145/3109984.3109985

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents