Optimizing Transfers of Control in the Static Pipeline Architecture
Authors: 
Ryan Baird, Peter Gavin, 
Magnus Själander, David Whalley, Gang-Ryung UhAuthors Info & Claims
Ryan Baird, Peter Gavin, Magnus Själander, David Whalley, Gang-Ryung UhAuthors Info & ClaimsArticle No.: 1, Pages 1 - 10
Abstract
Statically pipelined processors offer a new way to improve the performance beyond that of a traditional in-order pipeline while simultaneously reducing energy usage by enabling the compiler to control more fine-grained details of the program execution. This paper describes how a compiler can exploit the features of the static pipeline architecture to apply optimizations on transfers of control that are not possible on a conventional architecture. The optimizations presented in this paper include hoisting the target address calculations for branches, jumps, and calls out of loops, performing branch chaining between calls and jumps, hoisting the setting of return addresses out of loops, and exploiting conditional calls and returns. The benefits of performing these transfer of control optimizations include a 6.8% reduction in execution time and a 3.6% decrease in estimated energy usage.
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Published In
May 2015
141 pages
June 2015149 pagesISBN:9781450332576DOI:10.1145/2670529- General Chair:
- Sam H. Noh,
- Program Chairs:
- Sebastian Fischmeister,
- Jason Xue
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Published: 04 June 2015
Published in SIGPLAN Volume 50, Issue 5
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