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A Compile-Time Optimization Method for WCET Reduction in Real-Time Embedded Systems through Block Formation

Authors:

Morteza Mohajjel Kafshdooz,

Mohammadkazem Taram,

Alireza EjlaliAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 12, Issue 4

Article No.: 66, Pages 1 - 25

https://doi.org/10.1145/2845083

Published: 04 January 2016 Publication History

Abstract

Compile-time optimizations play an important role in the efficient design of real-time embedded systems. Usually, compile-time optimizations are designed to reduce average-case execution time (ACET). While ACET is a main concern in high-performance computing systems, in real-time embedded systems, concerns are different and worst-case execution time (WCET) is much more important than ACET. Therefore, WCET reduction is more desirable than ACET reduction in many real-time embedded systems. In this article, we propose a compile-time optimization method aimed at reducing WCET in real-time embedded systems. In the proposed method, based on the predicated execution capability of embedded processors, program code blocks that are in the worst-case paths of the program are merged to increase instruction-level parallelism and opportunity for WCET reduction. The use of predicated execution enables merging code blocks from different worst-case paths that can be very effective in WCET reduction. The experimental results show that the proposed method can reduce WCET by up to 45% as compared to previous compile-time block formation methods. It is noteworthy that compared to previous works, while the proposed method usually achieves more WCET reduction, it has considerably less negative impact on ACET and code size.

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Index Terms

A Compile-Time Optimization Method for WCET Reduction in Real-Time Embedded Systems through Block Formation
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 12, Issue 4

January 2016

848 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2836331

Editor:
Koen De Bosschere
Ghent University

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Copyright © 2016 ACM.

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Publication History

Published: 04 January 2016

Accepted: 01 November 2015

Revised: 01 October 2015

Received: 01 April 2014

Published in TACO Volume 12, Issue 4

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Cited By

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https://doi.org/10.3390/s24072365
Maroun ESchoeberl MPuschner P(2024)Predictable and optimized single-path code for predicated processorsJournal of Systems Architecture10.1016/j.sysarc.2024.103214154(103214)Online publication date: Sep-2024
https://doi.org/10.1016/j.sysarc.2024.103214
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https://doi.org/10.1016/j.array.2023.100282
Benz JBringmann O(2021)Scenario-Aware Program Specialization for Timing PredictabilityACM Transactions on Architecture and Code Optimization10.1145/347333318:4(1-26)Online publication date: 3-Sep-2021
https://dl.acm.org/doi/10.1145/3473333
Maroun ESchoeberl MPuschner P(2020)Towards Dual-Issue Single-Path Code2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC49007.2020.00039(176-183)Online publication date: May-2020
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Su XWu HXue JChen JShrivastava A(2019)WCET-aware hyper-block construction for clustered VLIW processorsProceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3316482.3326349(110-122)Online publication date: 23-Jun-2019
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Taram MVenkat ATullsen DBahar IHerlihy MWitchel ELebeck A(2019)Context-Sensitive FencingProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304060(395-410)Online publication date: 4-Apr-2019
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Yildiz AIskender DOzlu GUgurdag HAktemur BGoren S(2019)Software UART: A Use Case for VSCPU Worst-Case Execution Time Analyzer2019 4th International Conference on Computer Science and Engineering (UBMK)10.1109/UBMK.2019.8907220(504-509)Online publication date: Sep-2019
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Su XWu HXue J(2017)An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW ProcessorsACM Transactions on Embedded Computing Systems10.1145/312652416:5s(1-21)Online publication date: 27-Sep-2017
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