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A Compiler Approach for Exploiting Partial SIMD Parallelism

Authors:

Jingling XueAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 13, Issue 1

Article No.: 11, Pages 1 - 26

https://doi.org/10.1145/2886101

Published: 28 March 2016 Publication History

Abstract

Existing vectorization techniques are ineffective for loops that exhibit little loop-level parallelism but some limited superword-level parallelism (SLP). We show that effectively vectorizing such loops requires partial vector operations to be executed correctly and efficiently, where the degree of partial SIMD parallelism is smaller than the SIMD datapath width. We present a simple yet effective SLP compiler technique called Paver (PArtial VEctorizeR), formulated and implemented in LLVM as a generalization of the traditional SLP algorithm, to optimize such partially vectorizable loops. The key idea is to maximize SIMD utilization by widening vector instructions used while minimizing the overheads caused by memory access, packing/unpacking, and/or masking operations, without introducing new memory errors or new numeric exceptions. For a set of 9 C/C++/Fortran applications with partial SIMD parallelism, Paver achieves significantly better kernel and whole-program speedups than LLVM on both Intel’s AVX and ARM’s NEON.

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Index Terms

A Compiler Approach for Exploiting Partial SIMD Parallelism
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation

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Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 13, Issue 1

April 2016

347 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2899032

Editor:
Koen De Bosschere
Ghent University

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Copyright © 2016 ACM.

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Publication History

Published: 28 March 2016

Accepted: 01 January 2016

Revised: 01 November 2015

Received: 01 August 2015

Published in TACO Volume 13, Issue 1

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https://dl.acm.org/doi/10.1145/3620666.3651333
Guan XZhou HBao GLi HZhu LYao J(2024)PresCount: Effective Register Allocation for Bank Conflict Reduction2024 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)10.1109/CGO57630.2024.10444841(170-181)Online publication date: 2-Mar-2024
https://doi.org/10.1109/CGO57630.2024.10444841
Zhang ZOu YLiu YWang CZhou YWang XZhang YOuyang YShan JWang YXue JCui HFeng XAamodt TJerger NSwift M(2023)Occamy: Elastically Sharing a SIMD Co-processor across Multiple CPU CoresProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582046(483-497)Online publication date: 25-Mar-2023
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