research-article

Fine-Grained Interconnect Synthesis

Authors:

David Biancolin,

Jonathan RoseAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 9, Issue 4

Article No.: 31, Pages 1 - 22

https://doi.org/10.1145/2892641

Published: 11 August 2016 Publication History

Abstract

One of the key challenges for the FPGA industry going forward is to make the task of designing hardware easier. A significant portion of that design task is the creation of the interconnect pathways between functional structures. We present a synthesis tool that automates this process and focuses on the interconnect needs in the fine-grained (sub-IP-block) design space. Here there are several issues that prior research and tools do not address well: the need to have fixed, deterministic latency between communicating units (to enable high-performance local communication without the area overheads of latency insensitivity), and the ability to avoid generating unnecessary arbitration hardware when the application design can avoid it. Using a design example, our tool generates interconnect that requires 69% fewer lines of specification code than a handwritten Verilog implementation, which is a 32% overall reduction for the entire application. The resulting system, while requiring 6% more total functional and interconnect area, achieves the same performance. We also show a quantitative and qualitative advantages against an existing commercial interconnect synthesis tool, over which we achieve a 25% performance advantage and 15%/57% logic/memory area savings.

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Cited By

Volz DSpang CKoch A(2022)IPEC: Open-Source Design Automation for Inter-Processing Element CommunicationApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-031-19983-7_10(134-149)Online publication date: 27-Oct-2022
https://doi.org/10.1007/978-3-031-19983-7_10
Abbas MBetz V(2018)Latency Insensitive Design Styles for FPGAs2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00068(360-3607)Online publication date: Aug-2018
https://doi.org/10.1109/FPL.2018.00068

Index Terms

Fine-Grained Interconnect Synthesis
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Hardware accelerators
2. Networks
  1. Network properties
    1. Network structure
      1. Topology analysis and generation
  2. Network types
    1. Network on chip

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 9, Issue 4

Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015

September 2016

161 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/2984740

Editor:
Steve Wilton
Department of Electrical and Computer Engineering/University of British Columbia/Kaiser 4112, 5500-2332 Main Mall/Vancouver, BC V6T 1Z4 Canada

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Copyright © 2016 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 August 2016

Accepted: 01 February 2016

Revised: 01 December 2015

Received: 01 August 2015

Published in TRETS Volume 9, Issue 4

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Cited By

Volz DSpang CKoch A(2022)IPEC: Open-Source Design Automation for Inter-Processing Element CommunicationApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-031-19983-7_10(134-149)Online publication date: 27-Oct-2022
https://doi.org/10.1007/978-3-031-19983-7_10
Abbas MBetz V(2018)Latency Insensitive Design Styles for FPGAs2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00068(360-3607)Online publication date: Aug-2018
https://doi.org/10.1109/FPL.2018.00068

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