research-article

Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory

Authors:

Tseng-Yi Chen,

Yuan-Hao Chang,

Chien-Chung Ho,

Shuo-Han ChenAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 92, Pages 1 - 6

https://doi.org/10.1145/2897937.2898018

Published: 05 June 2016 Publication History

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Abstract

3D NAND has been proposed to provide a large capacity storage with low-cost consideration due to its high density memory architecture. However, 3D NAND needs to consume enormous time for garbage collection because of live-page copying overhead and long block erase time. To alleviate the impact of live-page copying on the performance of 3D NAND, a sub-block erase design has been designed. With sub-block erase design, this paper proposes a performance booster strategy to extremely boost the performance of garbage collection. As experimental results shows, the proposed strategy has a significant improvement on the average response time.

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DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 05 June 2016

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Ministry of Science and Technology, Taiwan

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Lee HChoi WHong Y(2023)On-Demand Garbage Collection Algorithm with Prioritized Victim Blocks for SSDsElectronics10.3390/electronics1209214212:9(2142)Online publication date: 7-May-2023
https://doi.org/10.3390/electronics12092142
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Dharamjeet Chen YChen TKuan YChang Y(2022)LLSM: A Lifetime-Aware Wear-Leveling for LSM-Tree on NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319754241:11(3946-3956)Online publication date: Nov-2022
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High-performance NAND and PRAM hybrid storage design for consumer electronics

Garbage Collection Algorithms for NAND Flash Memory Devices -- An Overview

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