research-article

DCC: Double Capacity Cache Architecture for Narrow-Width Values

Authors:

Tajana RosingAuthors Info & Claims

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

Pages 113 - 116

https://doi.org/10.1145/2902961.2902990

Published: 18 May 2016 Publication History

Abstract

Modern caches are designed to hold 64-bits wide data, however a proportion of data in the caches continues to be narrow width. In this paper, we propose a new cache architecture which increases the effective cache capacity up to 2X for the systems with narrow-width values, while also improving its power efficiency, bandwidth, and reliability. The proposed double capacity cache (DCC) architecture uses a fast and efficient peripheral circuitry to store two narrow-width values in a single wordline. In order to minimize the latency overhead in workloads without narrow-width data, the flag bits are added to tag store. The proposed DCC architecture decreases cache miss-rate by 50%, which results in 27% performance improvement and 30% higher dynamic energy efficiency. To improve reliability, DCC modifies the data distribution on individual bits, which results in 20% and 25% average static-noise margin (SNM) improvement in L1 and L2 caches respectively.

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Cited By

Choi JPark H(2021)Exploiting Bit-Level Write Patterns to Reduce Energy Consumption in Hybrid Cache ArchitectureIEICE Electronics Express10.1587/elex.18.20210327Online publication date: 2021
https://doi.org/10.1587/elex.18.20210327
Linhares ARusa HFormiga DAzevedo R(2020)A SystemC profiling framework to improve fixed-point hardware utilization2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI50935.2020.9189919(1-6)Online publication date: Aug-2020
https://doi.org/10.1109/SBCCI50935.2020.9189919
Rohbani NGau HMohammadinejad SMaiti TNavarro DMiura-Mattausch MMattausch HTakatsuka H(2019)Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width ValuesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.290948827:7(1675-1684)Online publication date: Jul-2019
https://doi.org/10.1109/TVLSI.2019.2909488
Show More Cited By

Index Terms

DCC: Double Capacity Cache Architecture for Narrow-Width Values
1. Hardware

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cover image ACM Conferences

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

May 2016

462 pages

ISBN:9781450342742

DOI:10.1145/2902961

General Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA
,
Program Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 May 2016

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GLSVLSI '16

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GLSVLSI '16: Great Lakes Symposium on VLSI 2016

May 18 - 20, 2016

Massachusetts, Boston, USA

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GLSVLSI '16 Paper Acceptance Rate 50 of 197 submissions, 25%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Choi JPark H(2021)Exploiting Bit-Level Write Patterns to Reduce Energy Consumption in Hybrid Cache ArchitectureIEICE Electronics Express10.1587/elex.18.20210327Online publication date: 2021
https://doi.org/10.1587/elex.18.20210327
Linhares ARusa HFormiga DAzevedo R(2020)A SystemC profiling framework to improve fixed-point hardware utilization2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI50935.2020.9189919(1-6)Online publication date: Aug-2020
https://doi.org/10.1109/SBCCI50935.2020.9189919
Rohbani NGau HMohammadinejad SMaiti TNavarro DMiura-Mattausch MMattausch HTakatsuka H(2019)Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width ValuesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.290948827:7(1675-1684)Online publication date: Jul-2019
https://doi.org/10.1109/TVLSI.2019.2909488
Carvalho AAzevedo R(2019)Towards a Transprecision Polymorphic Floating-Point Unit for Mixed-Precision Computing2019 31st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/SBAC-PAD.2019.00022(56-63)Online publication date: Oct-2019
https://doi.org/10.1109/SBAC-PAD.2019.00022
Rohbani NKumar Maiti TNavarro DMiura-Mattausch MMattausch HTakatsuka H(2019)NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00040(264-272)Online publication date: Nov-2019
https://doi.org/10.1109/ICCD46524.2019.00040
Khoshavi NDemara R(2018)Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy OptimizationIEEE Access10.1109/ACCESS.2018.28136686(14576-14590)Online publication date: 2018
https://doi.org/10.1109/ACCESS.2018.2813668
Imani MRahimi AKim YRosing T(2016)A low-power hybrid magnetic cache architecture exploiting narrow-width values2016 5th Non-Volatile Memory Systems and Applications Symposium (NVMSA)10.1109/NVMSA.2016.7547174(1-6)Online publication date: Aug-2016
https://doi.org/10.1109/NVMSA.2016.7547174

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