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Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs

Published: 23 May 2016 Publication History

Abstract

Different applications concurrently running on modern MPSoCs can interfere with each other when they use shared resources. This interference can cause side channels, i.e., sources of unintended information flow between applications. To prevent such side channels, we propose a hybrid mapping methodology that attempts to ensure spatial isolation, i.e., a mutually-exclusive allocation of resources to applications in the MPSoC. At design time and as a first step, we compute compact and connected application mappings (called shapes). In a second step, run-time management uses this information to map multiple spatially segregated shapes to the architecture. We present and evaluate a (fast) heuristic and an (exact) SAT-based mapper, demonstrating the viability of the approach.

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  • (2024)Methodologies for Design Space ExplorationHandbook of Computer Architecture10.1007/978-981-97-9314-3_23(915-945)Online publication date: 21-Dec-2024
  • (2022)mpsym: Improving Design-Space Exploration of Clustered Manycores With Arbitrary TopologiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310251241:6(1592-1605)Online publication date: Jul-2022
  • (2022)Model-based configuration of access protection units for multicore processors in embedded systemsMicroprocessors & Microsystems10.1016/j.micpro.2021.10437787:COnline publication date: 9-Apr-2022
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  1. Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs

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        cover image ACM Other conferences
        SCOPES '16: Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems
        May 2016
        211 pages
        ISBN:9781450343206
        DOI:10.1145/2906363
        • Editor:
        • Sander Stuijk
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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        • EDAA: European Design Automation Association
        • SIGBED

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        Published: 23 May 2016

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        Author Tags

        1. DSE
        2. Design Time
        3. Hybrid Mapping
        4. NoC
        5. Run Time
        6. Security
        7. Side Channel Attack

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        Overall Acceptance Rate 38 of 79 submissions, 48%

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        Cited By

        View all
        • (2024)Methodologies for Design Space ExplorationHandbook of Computer Architecture10.1007/978-981-97-9314-3_23(915-945)Online publication date: 21-Dec-2024
        • (2022)mpsym: Improving Design-Space Exploration of Clustered Manycores With Arbitrary TopologiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310251241:6(1592-1605)Online publication date: Jul-2022
        • (2022)Model-based configuration of access protection units for multicore processors in embedded systemsMicroprocessors & Microsystems10.1016/j.micpro.2021.10437787:COnline publication date: 9-Apr-2022
        • (2022)Methodologies for Design Space ExplorationHandbook of Computer Architecture10.1007/978-981-15-6401-7_23-1(1-31)Online publication date: 27-Jan-2022
        • (2022)QoS Aware Design-Time/Run-Time Manager for FPGA-Based Embedded SystemsDesign and Architecture for Signal and Image Processing10.1007/978-3-031-12748-9_8(96-107)Online publication date: 30-Jul-2022
        • (2022)Embeddings of Task Mappings to Multicore SystemsEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-04580-6_11(161-176)Online publication date: 27-Apr-2022
        • (2021)Software Compilation and Optimization Techniques for Heterogeneous Multi‐core PlatformsMulti‐Processor System‐on‐Chip 210.1002/9781119818410.ch10(203-235)Online publication date: 28-Apr-2021
        • (2020)Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future PerspectiveJournal of Low Power Electronics and Applications10.3390/jlpea1004003810:4(38)Online publication date: 17-Nov-2020
        • (2020)A Case for Security-Aware Design-Space Exploration of Embedded SystemsJournal of Low Power Electronics and Applications10.3390/jlpea1003002210:3(22)Online publication date: 17-Jul-2020
        • (2019)On Compact Mappings for Multicore SystemsEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_23(325-335)Online publication date: 8-Aug-2019
        • Show More Cited By

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