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Optimization Models for Three On-Chip Network Problems

Authors:

Michael C. Ferris,

David A. WoodAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 13, Issue 3

Article No.: 26, Pages 1 - 27

https://doi.org/10.1145/2943781

Published: 17 September 2016 Publication History

Abstract

We model three on-chip network design problems—memory controller placement, resource allocation in heterogeneous on-chip networks, and their combination—as mathematical optimization problems. We model the first two problems as mixed integer linear programs. We model the third problem as a mixed integer nonlinear program, which we then linearize exactly. Sophisticated optimization algorithms enable solutions to be obtained much more efficiently. Detailed simulations using synthetic traffic and benchmark applications validate that our designs provide better performance than solutions proposed previously. Our work provides further evidence toward suitability of optimization models in searching/pruning architectural design space.

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Cited By

Green CThottethodi M(2024)NetSmith: An Optimization Framework for Machine-Discovered Network TopologiesProceedings of the 53rd International Conference on Parallel Processing10.1145/3673038.3673060(421-432)Online publication date: 12-Aug-2024
https://dl.acm.org/doi/10.1145/3673038.3673060
Lu ZYao Y(2017)Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFSIEEE Transactions on Computers10.1109/TC.2017.271501866:11(1903-1917)Online publication date: 6-Oct-2017
https://dl.acm.org/doi/10.1109/TC.2017.2715018
Le TNing RZhao DWu HBayoumi M(2017)Optimizing the heterogeneous network on-chip design in manycore architectures2017 30th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2017.8226033(184-189)Online publication date: Sep-2017
https://doi.org/10.1109/SOCC.2017.8226033
Show More Cited By

Index Terms

Optimization Models for Three On-Chip Network Problems
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
      2. Multicore architectures

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Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 13, Issue 3

September 2016

207 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2988523

Editor:
Koen De Bosschere
Ghent University

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Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 17 September 2016

Accepted: 01 May 2016

Revised: 01 March 2016

Received: 01 November 2015

Published in TACO Volume 13, Issue 3

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Air Force Office of Scientific Research
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U.S. Department of Energy, Office of Science, Office of Advanced Scientific Computing Research

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Cited By

Green CThottethodi M(2024)NetSmith: An Optimization Framework for Machine-Discovered Network TopologiesProceedings of the 53rd International Conference on Parallel Processing10.1145/3673038.3673060(421-432)Online publication date: 12-Aug-2024
https://dl.acm.org/doi/10.1145/3673038.3673060
Lu ZYao Y(2017)Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFSIEEE Transactions on Computers10.1109/TC.2017.271501866:11(1903-1917)Online publication date: 6-Oct-2017
https://dl.acm.org/doi/10.1109/TC.2017.2715018
Le TNing RZhao DWu HBayoumi M(2017)Optimizing the heterogeneous network on-chip design in manycore architectures2017 30th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2017.8226033(184-189)Online publication date: Sep-2017
https://doi.org/10.1109/SOCC.2017.8226033
Le TZhao DBayoumi M(2017)Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware Approach2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.83(439-444)Online publication date: Jul-2017
https://doi.org/10.1109/ISVLSI.2017.83

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