Article

Free access

Timing driven maze routing

Authors:

Sung-Woo Hur,

Ashok Jagannathan,

John LillisAuthors Info & Claims

ISPD '99: Proceedings of the 1999 international symposium on Physical design

Pages 208 - 213

https://doi.org/10.1145/299996.300079

Published: 12 April 1999 Publication History

PDF eReader

References

[1]

C. Y. Lee, "An Algorithm for Path Connection and Its Applications," IRE Trans. on Electronic Computers, vol. EC-10, no. 3, pp. 346-365, 1961.

Crossref

Google Scholar

[2]

E.F. Moore, "Shortest Path through a Maze," in Proc. of the International ~ymposiun on Switching Circuits, Harvard University Press, Cambridge, MA, 1959. (in Annals of the Harvard Computing Laboratory, Vol 30, .Part II).

Google Scholar

[3]

J. Lillis and P. Buch, "T~ble-Lookup Methods for Improved Performance-Driven Routing," in $SfX DAU, pp. 368-377, 1998.

Digital Library

Google Scholar

[4]

H.-P. Tseng, L. Scheffer, and C. Sechen, "Timing and Crosstalk Driven Area Routing," in $Sth DAC, pp. 378-381, 1998.

Digital Library

Google Scholar

[5]

T. Xue, E. Kuh, and D. Wang, "Post GlobM RoUting CrosstMk Risk Estimation and Reduction," in ICCAD, pp. 302-309, IEEE Computer Society Press, 1996.

Digital Library

Google Scholar

[6]

H. Zhou and D. Wong, "Global Routing with Crosstalk Constraints," in 35th DAC, pp. 374-377, 1998.

Digital Library

Google Scholar

[7]

E. W. Dijkstra, A Discipline of Programming. Prentice-Hall, Englewood Cliffs, N.J., 1976.

Digital Library

Google Scholar

[8]

W. C. Elmore, "The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifiers," J. Applied Physics, vol. 19, pp. 55-63, 1948.

Crossref

Google Scholar

[9]

J. P. Fishburn and C. Schevon, "Shaping A Distributed-RC Lint to Minimize Elmore Delay," IEEE Trans. on Circuits and Systems-Is Fundamental Theory and Applications, vol. 42, no. 12, pp. 1020- 1022, 1995.

Crossref

Google Scholar

[10]

Y.-P. C. Chung-Ping Chen and D. F. Wong, "Optimal Wire-Sizing Formula Under the Elmore Delay Model," in DAC, pp. 487-490, 1996.

Digital Library

Google Scholar

[11]

M. Kang, W.-M. Dai, T. Dillinger, and D. LaPotin, "Delay Bounded Buffered Tree Construction for Timing Driven Floorplanning," in ICCAD, pp. 707-712, 1997.

Digital Library

Google Scholar

[12]

J. LiUis, C.-K. Cheng, T.-T. Y. Lin, and C.-Y. Ho, "New Techniques for Performance Driven Routing with Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing," in 33rd A CM/IEEE DA C, pp. 395-400, 1996.

Digital Library

Google Scholar

Cited By

View all

Al-Assadi WKakarla S(2008)A BIST Technique for Crosstalk Noise Detection in FPGAsProceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems10.1109/DFT.2008.14(167-175)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.1109/DFT.2008.14
Kakarla SAl-Assadi W(2007)A Framework for the Detection of Crosstalk Noise in FPGAs2007 IEEE Region 5 Technical Conference10.1109/TPSD.2007.4380383(211-216)Online publication date: Apr-2007
https://doi.org/10.1109/TPSD.2007.4380383
Alpert CHu JSapatnekar SVillarrubia P(2006)A practical methodology for early buffer and wire resource allocationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2003.81074922:5(573-583)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2003.810749
Show More Cited By

Index Terms

Timing driven maze routing

Recommendations

Timing driven track routing considering coupling capacitance
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven routing. In this paper, a coupling aware timing driven track routing heuristic is ...
Vision-based maze navigation for humanoid robots

We present a vision-based approach for navigation of humanoid robots in networks of corridors connected through curves and junctions. The objective of the humanoid is to follow the corridors, walking as close as possible to their center to maximize ...
Timing- and crosstalk-driven area routing

We present a timing- and crosstalk-driven router for the chip assembly task that is applied between global and detailed routing. Our new approach aims to process the crosstalk and timing constraints by ordering nets and tuning wire spacing in a ...

Comments

Information & Contributors

Information

Published In

ISPD '99: Proceedings of the 1999 international symposium on Physical design

April 1999

223 pages

ISBN:1581130899

DOI:10.1145/299996

Chairman:
D. F. Wong
Univ. of Texas-Austin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 April 1999

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ISPD99

Sponsor:

SIGDA

ISPD99: 1999 International Symposium on Physical Design

April 12 - 14, 1999

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
380
Total Downloads

Downloads (Last 12 months)61
Downloads (Last 6 weeks)13

Reflects downloads up to 25 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Al-Assadi WKakarla S(2008)A BIST Technique for Crosstalk Noise Detection in FPGAsProceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems10.1109/DFT.2008.14(167-175)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.1109/DFT.2008.14
Kakarla SAl-Assadi W(2007)A Framework for the Detection of Crosstalk Noise in FPGAs2007 IEEE Region 5 Technical Conference10.1109/TPSD.2007.4380383(211-216)Online publication date: Apr-2007
https://doi.org/10.1109/TPSD.2007.4380383
Alpert CHu JSapatnekar SVillarrubia P(2006)A practical methodology for early buffer and wire resource allocationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2003.81074922:5(573-583)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2003.810749
Kastner RBozorgzadeh ESarrafzadeh M(2006)Pattern routingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2002.101389121:7(777-790)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2002.1013891
Alpert CGandham GHu JNeves JQuay SSapatnekar S(2006)Steiner tree optimization for buffers, blockages, and baysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.91821320:4(556-562)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.918213
Smey RSwartz BMadden P(2003)Crosstalk Reduction in Area RoutingProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022832Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022832
Smey RSwartz BMadden P(2003)Crosstalk reduction in area routing2003 Design, Automation and Test in Europe Conference and Exhibition10.1109/DATE.2003.1253714(862-867)Online publication date: 2003
https://doi.org/10.1109/DATE.2003.1253714
Hu JSapatnekar S(2001)A survey on multi-net global routing for integrated circuitsIntegration10.1016/S0167-9260(01)00020-731:1(1-49)Online publication date: Nov-2001
https://doi.org/10.1016/S0167-9260(01)00020-7

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Timing driven track routing considering coupling capacitance

Vision-based maze navigation for humanoid robots

Timing- and crosstalk-driven area routing

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

References

Cited By

Index Terms

Recommendations

Timing driven track routing considering coupling capacitance

Vision-based maze navigation for humanoid robots

Timing- and crosstalk-driven area routing

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Login options

Full Access

Share

Share this Publication link

Share on social media

Affiliations