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Throughput Propagation in Constraint-Based Design Space Exploration for Mixed-Criticality Systems

Published: 23 January 2017 Publication History

Abstract

When designing complex mixed-critical systems on multiprocessor platforms, a huge number of design alternatives has to be evaluated. Therefore, there is a need for tools which systematically find and analyze the ample alternatives and identify solutions that satisfy the design constraints. The recently proposed design space exploration (DSE) tool DeSyDe uses constraint programming (CP) to find implementations with performance guarantees for multiple applications with potentially mixed-critical design constraints on a shared platform. A key component of the DeSyDe tool is its throughput analysis component, called a throughput propagator in the context of CP. The throughput propagator guides the exploration by evaluating each design decision and is therefore executed excessively throughout the exploration. This paper presents two throughput propagators based on different analysis methods for DeSyDe. Their performance is evaluated in a range of experiments with six different application graphs, heterogeneous platform models and mixed-critical design constraints. The results suggest that the MCR throughput propagator is more efficient.

References

[1]
A. Bonfietti, L. Benini, M. Lombardi, and M. Milano. An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms. In DATE, pages 897--902, 2010.
[2]
A. Bonfietti, M. Lombardi, M. Milano, and L. Benini. Throughput constraint for synchronous data flow graphs. In Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, pages 26--40. Springer Berlin Heidelberg, 2009.
[3]
Boost Graph Library. http://www.boost.org. Accessed: 2016-11-20.
[4]
G. C. Buttazzo. Hard Real-time Computing Systems: Predictable Scheduling Algorithms And Applications. Springer, Santa Clara, CA, USA, 2011.
[5]
A. Dasdan and R. Gupta. Faster maximum and minimum mean cycle algorithms for system-performance analysis. IEEE TCAD, 17(10):889--899, 1998.
[6]
R. de Groote, P. K. F. Hölzenspies, J. Kuper, and H. Broersma. Back to basics: Homogeneous representations of multi-rate synchronous dataflow graphs. In MEMCODE'13, pages 35--46, 2013.
[7]
R. De Groote, J. Kuper, H. Broersma, and G. J. Smit. Max-plus algebraic throughput analysis of synchronous dataflow graphs. In EUROMICRO-SEAA, pages 29--38, 2012.
[8]
DeSyDe. https://github.com/forsyde/DeSyDe. Accessed: 2016-11-10.
[9]
M. Fakih, K. Grüttner, M. Fränzle, and A. Rettberg. Towards performance analysis of SDFGs mapped to shared--bus architectures using model--checking. In DATE, 2013.
[10]
A. H. Ghamarian, M. Geilen, S. Stuijk, T. Basten, A. Moonen, M. J. Bekooij, B. D. Theelen, and M. Mousavi. Throughput analysis of synchronous data flow graphs. In ACSD, pages 25--36, 2006.
[11]
A. Hansson, K. Goossens, M. Bekooij, and J. Huisken. CoMPSoC: A template for composable and predictable multi-processor system on chips. ACM TODAES, 14(1):2:1--2:24, Jan. 2009.
[12]
K. Ito and K. K. Parhi. Determining the minimum iteration period of an algorithm. VLSI Signal Processing, 11(3):229--244, 1995.
[13]
N. Khalilzad, K. Rosvall, and I. Sander. A modular design space exploration framework for multiprocessor real-time systems. In FDL, September 2016.
[14]
E. A. Lee and D. G. Messerschmitt. Synchronous data flow. In Proceedings of the IEEE, volume 75 of 9, pages 1235--1245, September 1987.
[15]
E. A. Lee and A. Sangiovanni-Vincentelli. A framework for comparing models of computation. IEEE TCAD, 17(12):1217--1229, Dec. 1998.
[16]
B. Lickly, I. Liu, S. Kim, H. D. Patel, S. A. Edwards, and E. A. Lee. Predictable programming on a precision timed architecture. In CASES, pages 137--146, New York, NY, USA, 2008. ACM.
[17]
U. M. Mirza, F. Gruian, and K. Kuchcinski. Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chip. CEE, 40(8):276--291, 2014.
[18]
O. Moreira, J.-D. Mol, M. Bekooij, and J. Van Meerbergen. Multiprocessor resource allocation for hard-real-time streaming with a dynamic job-mix. In IEEE RTAS, pages 332--341, 2005.
[19]
C. Pitter and M. Schoeberl. A real-time Java chip-multiprocessor. ACM TECS, 10(1):9:1--9:34, Aug. 2010.
[20]
K. Rosvall and I. Sander. A constraint-based design space exploration framework for real-time applications on MPSoCs. In DATE, pages 1--6, 2014.
[21]
C. Schulte, G. Tack, and M. Z. Lagerkvist. Modeling and Programming with Gecode, 2016. http://www.gecode.org/.
[22]
S. Sriram and S. S. Bhattacharyya. Embedded Multiprocessors: Scheduling and Synchronization. Marcel Dekker, Inc., New York, NY, USA, 2000.
[23]
S. Stuijk, T. Basten, M. Geilen, and H. Corporaal. Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs. In DAC, pages 777--782, 2007.
[24]
R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, et al. The worst-case execution-time problem---overview of methods and survey of tools. ACM TECS, 7(3):1--53, 2008.
[25]
J. Zhu, I. Sander, and A. Jantsch. Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. In DATE, pages 1506--1511, 2009.
[26]
J. Zhu, I. Sander, and A. Jantsch. Constrained global scheduling of streaming applications on MPSoCs. In ASP-DAC, pages 223--228, 2010.

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  • (2024)IDeSyDe: Systematic Design Space Exploration via Design Space IdentificationACM Transactions on Design Automation of Electronic Systems10.1145/364764029:5(1-45)Online publication date: 10-Feb-2024
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  1. Throughput Propagation in Constraint-Based Design Space Exploration for Mixed-Criticality Systems

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      cover image ACM Other conferences
      RAPIDO '17: Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
      January 2017
      47 pages
      ISBN:9781450348409
      DOI:10.1145/3023973
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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      Published: 23 January 2017

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      Author Tags

      1. Constraint Programming
      2. Correct-by-Construction
      3. Design Space Exploration
      4. Performance Analysis

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      • Research-article
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      RAPIDO '17
      RAPIDO '17: Methods and Tools
      January 23 - 25, 2017
      Stockholm, Sweden

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      RAPIDO '17 Paper Acceptance Rate 6 of 12 submissions, 50%;
      Overall Acceptance Rate 14 of 28 submissions, 50%

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      Cited By

      View all
      • (2024)IDeSyDe: Systematic Design Space Exploration via Design Space IdentificationACM Transactions on Design Automation of Electronic Systems10.1145/364764029:5(1-45)Online publication date: 10-Feb-2024
      • (2024)Multi-objective preference-free exact design space exploration of static DSP on multicore platforms2024 Forum on Specification & Design Languages (FDL)10.1109/FDL63219.2024.10673877(1-9)Online publication date: 4-Sep-2024
      • (2021)Design Space Exploration for Secure IoT Devices and Cyber-Physical SystemsACM Transactions on Embedded Computing Systems10.1145/343037220:4(1-24)Online publication date: 29-May-2021
      • (2020)Towards Security Attack and Risk Assessment during Early System Design2020 International Conference on Cyber Security and Protection of Digital Services (Cyber Security)10.1109/CyberSecurity49315.2020.9138896(1-8)Online publication date: Jun-2020
      • (2020)A Design Exploration Framework for Secure IoT-Systems2020 International Conference on Cyber Situational Awareness, Data Analytics and Assessment (CyberSA)10.1109/CyberSA49311.2020.9139631(1-8)Online publication date: Jun-2020
      • (2020)An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor SystemArabian Journal for Science and Engineering10.1007/s13369-020-04634-zOnline publication date: 26-May-2020
      • (2019)Security Driven Design Space Exploration for Embedded Systems2019 Forum for Specification and Design Languages (FDL)10.1109/FDL.2019.8876944(1-8)Online publication date: Sep-2019
      • (2019)HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions2019 22nd Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2019.00085(554-561)Online publication date: Aug-2019
      • (2019)Consideration of Security Attacks in the Design Space Exploration of Embedded Systems2019 22nd Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2019.00082(530-537)Online publication date: Aug-2019
      • (2018)Criticality-aware Design Space Exploration for Mixed-Criticality Embedded SystemsCompanion of the 2018 ACM/SPEC International Conference on Performance Engineering10.1145/3185768.3185769(45-46)Online publication date: 2-Apr-2018
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