research-article

Physical Design Considerations of One-level RRAM-based Routing Multiplexers

Authors:

Edouard Giacomin,

Giovanni De Micheli,

Pierre-Emmanuel GaillardonAuthors Info & Claims

ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design

Pages 47 - 54

https://doi.org/10.1145/3036669.3036675

Published: 19 March 2017 Publication History

Abstract

Resistive Random Access Memory(RRAM) technology opens the opportunity for granting both high-performance and low-power features to routing multiplexers. In this paper, we study the physical design considerations related to RRAM-based routing multiplexers and particularly the integration of 4T(ransistor)1R(RAM) programming structures within their routing tree. We first analyze the limitations in the physical design of a naive one-level 4T1R-based multiplexer, such as co-integration of low-voltage nominal power supply and high voltage programming supply, as well as the use of long metal wires across different isolating wells. To address the limitations, we improve the one-level 4T1R-based multiplexer by re-arranging the nominal and programming voltage domains, and also study the optimal location of RRAMs in terms of performance. The improved design can effectively reduce the length of long metal wires by 50%. Electrical simulations show that using a 7nm FinFET transistor technology, the improved 4T1R-based multiplexers improve delay by 69% as compared to the basic design. At nominal working voltage, considering an input size ranging from 2 to 32, the improved 4T1R-based multiplexers outperform the best CMOS multiplexers in area by 1.4x, delay by 2x and power by 2x respectively. The improved 4T1R-based multiplexers operating at near-Vt regime can improve Power-Delay Product by up to 5.8x when compare to the best CMOS multiplexers working at nominal voltage.

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Cited By

Dongre ABoro BTrivedi G(2023)ADC-Less Reprogrammable RRAM Array Architecture for In-Memory ComputingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.331957831:12(2053-2060)Online publication date: Dec-2023
https://doi.org/10.1109/TVLSI.2023.3319578
Dongre ATrivedi G(2023)Variation Tolerant RRAM Based Synaptic Architecture for On-Chip TrainingIEEE Transactions on Nanotechnology10.1109/TNANO.2023.329896222(436-444)Online publication date: 2023
https://doi.org/10.1109/TNANO.2023.3298962
Rizzi TBaroni AGlukhov ABertozzi DWenger CIelmini DZambelli C(2023)Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAsIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2023.325901523:3(328-336)Online publication date: Sep-2023
https://doi.org/10.1109/TDMR.2023.3259015
Show More Cited By

Index Terms

Physical Design Considerations of One-level RRAM-based Routing Multiplexers
1. Hardware
  1. Emerging technologies
    1. Memory and dense storage
  2. Integrated circuits

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cover image ACM Conferences

ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design

March 2017

176 pages

ISBN:9781450346962

DOI:10.1145/3036669

General Chair:
Mustafa Ozdal
Bilkent University
,
Program Chair:
Chris Chu
Iowa State University

Copyright © 2017 ACM.

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Published: 19 March 2017

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ISPD '17: International Symposium on Physical Design

March 19 - 22, 2017

Oregon, Portland, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Dongre ABoro BTrivedi G(2023)ADC-Less Reprogrammable RRAM Array Architecture for In-Memory ComputingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.331957831:12(2053-2060)Online publication date: Dec-2023
https://doi.org/10.1109/TVLSI.2023.3319578
Dongre ATrivedi G(2023)Variation Tolerant RRAM Based Synaptic Architecture for On-Chip TrainingIEEE Transactions on Nanotechnology10.1109/TNANO.2023.329896222(436-444)Online publication date: 2023
https://doi.org/10.1109/TNANO.2023.3298962
Rizzi TBaroni AGlukhov ABertozzi DWenger CIelmini DZambelli C(2023)Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAsIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2023.325901523:3(328-336)Online publication date: Sep-2023
https://doi.org/10.1109/TDMR.2023.3259015
Rizzi TBaroni ABertozzi DWenger CIelmini DZambelli C(2023)Exploring the NBTI Aging and PVT effects on RRAM-based FPGA Multiplexers Performance2023 IEEE International Integrated Reliability Workshop (IIRW)10.1109/IIRW59383.2023.10477644(1-5)Online publication date: 8-Oct-2023
https://doi.org/10.1109/IIRW59383.2023.10477644
Rizzi TBaroni AGlukhov ABertozzi DWenger CIelmini DZambelli C(2022)Exploring Process-Voltage-Temperature Variations Impact on 4T1R Multiplexers for Energy-aware Resistive RAM-based FPGAs2022 IEEE International Integrated Reliability Workshop (IIRW)10.1109/IIRW56459.2022.10032753(1-5)Online publication date: 9-Oct-2022
https://doi.org/10.1109/IIRW56459.2022.10032753
Tang XGiacomin ECadareanu PGore GGaillardon PDi Natale GFummi F(2020)A RRAM-based FPGA for energy-efficient edge computingProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408384(144a-144f)Online publication date: 9-Mar-2020
https://dl.acm.org/doi/10.5555/3408352.3408384
Tang XGiacomin ECadareanu PGore GGaillardon P(2020)A RRAM-based FPGA for Energy-efficient Edge Computing2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116478(144-a-144-f)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116478
Levisse AGaillardon PGiraud BO'Connor INoel JMoreau MPortal J(2019)Resistive Switching Memory Architecture Based on Polarity Controllable SelectorsIEEE Transactions on Nanotechnology10.1109/TNANO.2018.288714018(183-194)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1109/TNANO.2018.2887140

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