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Dynamic removal of redundant computations

Authors:

Carlos Molina,

Antonio González, and

Jordi TubellaAuthors Info & Claims

ICS '99: Proceedings of the 13th international conference on Supercomputing

May 1999

Pages 474 - 481

https://doi.org/10.1145/305138.305239

Published: 01 May 1999 Publication History

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References

[1]

H. Abelson and G.J. Sussman, Structure and interpretation of Computer Programs, McGraw Hill, New York, I985

Digital Library

Google Scholar

[2]

M. Azam, P. Franzon and W. Liu, "Low Power Data Processing by Elimination of Redundant Computations", in Procs. Int. Syrup. on Low Power Electronics and Design, pp. 259-264, 1997

Digital Library

Google Scholar

[3]

D. Burger, TM. Austin and S. Bennet, "Evaluating Future Microprocessors: The SimpleScalar Tool Set". Technical Report CS-TR-96-1308. University of Wisconsin, July 1996

Google Scholar

[4]

A. Gonz~lez, J. Tubella and C. Molina, "The Performance Potential of Data Value Reuse", Technical Report UPC-DAC- 1998-23, Universitat Polit~cnica de Cataiunya, 1998

Google Scholar

[5]

S.H. Harbison, "An Architectural Alternative to Optimizing Compilers", in Procs. of lnt. Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 57- 65, 1982

Digital Library

Google Scholar

[6]

J. Huang and D. Lijla, "Exploiting Basic Block Value Locality with Block Reuse", in Procs. of 5th. Int. Syrup. on High-Performance Computer Architecture, 1999

Digital Library

Google Scholar

[7]

P. McNamee and M. Hall, "Developing a Tool for Memoizing Functions in C++", ACM SIGPLANNotices, vol. 33, n. 8, pp. 17-22, Aug. 1998

Digital Library

Google Scholar

[8]

S.F. Oberman and M.J. Flynn, "On Division and Reciprocal Caches", Technical Report CSL-TR-95-666, Stanford University, 1995

Digital Library

Google Scholar

[9]

S. E. Richardson, "Exploiting Trivial and Redundant Computations", in Procs. of Int. Symp. on Computer Arithmetic, pp. 220-227, 1993

Crossref

Google Scholar

[10]

S. E. Richardson, "Caching Function Results: Faster Arithmetic by Avoiding Unnecessary Computation", Technical Report SMLI TR-92-1, Sun Microsystems Laboratories, 1992

Digital Library

Google Scholar

[11]

A. Sodani and G.S. Sohi, "Dynamic Instruction Reuse", in Procs. of int. Syrup. on Computer Architecture, pp. 194-205, 1997

Digital Library

Google Scholar

[12]

A. Sodani and G.S. Sohi, "An Empirical Analysis of Instruction Repetition" in Procs. of Int. Conf. on Architectural Support for Programming Languages and Operating Systems ", 1998

Digital Library

Google Scholar

[13]

A. Sodani and G.S. Sob. i, "Understanding the Differences Between Value Prediction and Instruction. Reuse", in t~ocs. of 31st. Ann. Int. Syrup. on Microarchitecture, 1998

Digital Library

Google Scholar

[14]

G.S. Sohi, "instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers", IEEE Transactions on Computers, 39(3):349- 359, 1990.

Digital Library

Google Scholar

[15]

S.P. Song, M. Denman and J. Chang, "The PowerPC 604 RISC Microprocessor", IEEE Micro, 14(5):8-17, Oct. 1994

Digital Library

Google Scholar

[16]

N. Weinberg and D. Nagle, "Dynamic Elimination of Pointer- Expressions", in Procs. Int. Conf. on Parallel Architectures and Compilation Techniques, pp. 142-147, 1998

Digital Library

Google Scholar

[17]

T. Yeh and Y. N. Patt, "Alternative Implementations of Two- Level Adaptive Branch Prediction", In Procs. of the 19th Annual International Symposium on Computer Architecture, pp 124-134, 1992.

Digital Library

Google Scholar

Cited By

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Vicarte JShome PNayak NTrippel CMorrison AKohlbrenner DFletcher CMartínez JDuato JJohn L(2021)Opening pandora's boxProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00035(347-360)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00035
Radaideh AGratz P(2020)Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218547(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218547
Rouberte LSena ANery AMarzulo LAlves TFrança F(2018)DF‐DTM: Dynamic Task Memoization and reuse in dataflowConcurrency and Computation: Practice and Experience10.1002/cpe.493731:18Online publication date: 3-Sep-2018
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Index Terms

Dynamic removal of redundant computations

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Published In

ICS '99: Proceedings of the 13th international conference on Supercomputing

June 1999

509 pages

ISBN:158113164X

DOI:10.1145/305138

Chairmen:
Theodore Papatheodorou
Univ. of Patras, Patras, Greece
,
Mateo Valero
Univ. Politècnica de Catalunya, Barcelona, Spain
,
Constantine D. Polychronopoulos
Univ. of Illinois
,
Yoichi Muraoka
Waseda Univ.
,
Jesus Labarta
Univ. Politècnica de Catalunya, Barcelona, Spain

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1999

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ICS99

Sponsor:

SIGARCH

ICS99: The 13th ACM International Conference on Supercomputing

June 20 - 25, 1999

Rhodes, Greece

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ICS '99 Paper Acceptance Rate 57 of 180 submissions, 32%;

Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

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Vicarte JShome PNayak NTrippel CMorrison AKohlbrenner DFletcher CMartínez JDuato JJohn L(2021)Opening pandora's boxProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00035(347-360)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00035
Radaideh AGratz P(2020)Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218547(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218547
Rouberte LSena ANery AMarzulo LAlves TFrança F(2018)DF‐DTM: Dynamic Task Memoization and reuse in dataflowConcurrency and Computation: Practice and Experience10.1002/cpe.493731:18Online publication date: 3-Sep-2018
https://doi.org/10.1002/cpe.4937
J. Marzulo LC. Sena AS. Nery ABentes CM. Coelho IS. de Castro MT. Oliveira SA. O. Alves TM. G. França F(2018)DTM@GPU: Characterizing and evaluating trace redundancy in GPUConcurrency and Computation: Practice and Experience10.1002/cpe.445031:18Online publication date: 28-Feb-2018
https://doi.org/10.1002/cpe.4450
De Moura RTorres GPilla MPilla LDa Costa AFranca F(2016)Value Reuse Potential in ARM Architectures2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/SBAC-PAD.2016.30(174-181)Online publication date: Oct-2016
https://doi.org/10.1109/SBAC-PAD.2016.30
Mckeown MBalkind JWentzlaff DFlautner KWenisch TOzer EFerdman M(2014)Execution DraftingProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2014.43(432-444)Online publication date: 13-Dec-2014
https://dl.acm.org/doi/10.1109/MICRO.2014.43
Islam MStenstrom PGupta RMooney V(2011)A unified approach to eliminate memory accesses earlyProceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems10.1145/2038698.2038710(55-64)Online publication date: 9-Oct-2011
https://dl.acm.org/doi/10.1145/2038698.2038710
Sendag RLilja DYi J(2010)Instruction PrecomputationSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch10(245-267)Online publication date: 14-Jan-2010
https://doi.org/10.1201/9781420035155.ch10
Long GFranklin DBiswas SOrtiz POberg JFan DChong F(2010)Minimal Multi-threadingProceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2010.41(337-348)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1109/MICRO.2010.41
Golander AWeiss S(2009)Reexecution and Selective Reuse in Checkpoint ProcessorsTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_13(242-268)Online publication date: 22-Apr-2009
https://dl.acm.org/doi/10.1007/978-3-642-00904-4_13
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Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

An evaluation of speculative instruction execution on simultaneous multithreaded processors

Partial resolution for redundant operation table