research-article

Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning

Authors:

Mohamad Alawieh,

Xin LiAuthors Info & Claims

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Article No.: 9, Pages 1 - 6

https://doi.org/10.1145/3061639.3062235

Published: 18 June 2017 Publication History

Abstract

With the continuous drive towards integrated circuits scaling, efficient performance modeling is becoming more crucial yet, more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to 3.66x runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy.

References

[1]

Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2011.

[2]

X. Li, J. Le and L. Pileggi, Statistical Performance Modeling and Optimization, Now Publishers, 2007.

Digital Library

[3]

A. Singhee and R. Rutenbar, "Beyond low-order statistical response surfaces: latent variable regression for efficient, highly nonlinear fitting," DAC, pp. 256--261, 2007.

Digital Library

[4]

T. McConaghy and G. Gielen, "Template-free symbolic performance modeling of analog circuits via canonical-form functions and genetic programming," IEEE TCAD, vol. 28, no. 8, pp. 1162--1175, Aug. 2009.

Digital Library

[5]

T. McConaghy, T. Eeckelaert, and G. Gielen, "Template-free symbolic performance modeling of analog circuits via canonical-form functions and genetic programming," IEEE TCAD, vol. 28, no. 8, pp. 1162--1175, Aug. 2009.

Digital Library

[6]

X. Li, J. Le, P. Gopalakrishnan and L. Pileggi, "Asymptotic probability extraction for nonnormal performance distributions," IEEE TCAD, vol. 26, no. 1, pp. 16--37, Jan. 2007.

Digital Library

[7]

F. Gong, Y. Shi, H. Yu and L. He, "Variability-aware parametric yield estimation for analog/mixed-signal circuits: concepts, algorithms, and challenges," IEEE D&T, vol. 31, no. 4, pp. 6--15, Jan. 2014.

[8]

H. Zhang, H. Zhang, T. Chen, M. Ting and X. Li, "Efficient design-specific worst-case corner extraction for integrated circuits," DAC, pp. 386--389, 2009.

Digital Library

[9]

Y. Wang, M. Orshansky and C. Caramanis, "Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization," DAC, pp. 1--6, 2014.

Digital Library

[10]

M. B. Alawieh, F. Wang, R. Kanj, X. Li and R. Joshi, "Efficient analog circuit optimization using sparse regression and error margining," ISQED, pp. 410--415, 2016.

[11]

V. Natarajan, A. Banerjee, S. Sen, S. Devarakond and A. Chatterjee, "Yield recovery of RF transceiver systems using iterative tuning-driven power-conscious performance optimization," IEEE D&T, vol. 32, no. 1, pp. 61--69, Jan. 2015.

[12]

X. Li, W. Zhang and F. Wang, "Large-scale statistical performance modeling of analog and mixed-signal circuits," CICC, 2012.

[13]

X. Li, "Finding deterministic solution from underdetermined equation: large-scale performance modeling by least angle regression," DAC, pp. 364--369, 2009.

Digital Library

[14]

X. Li, "Finding deterministic solution from underdetermined equation: large-scale performance variability modeling of analog/RF circuits," IEEE TCAD, vol. 29, no. 11, pp. 1661--1668, Nov. 2010.

Digital Library

[15]

F. Wang, W. Zhang, S. Sun, X. Li and C. Gu, "Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data," DAC, pp. 1--6, 2013.

Digital Library

[16]

X. Li, F. Wang, S. Sun and C. Gu, "Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits," ICCAD, pp. 795--802, 2013.

Digital Library

[17]

Q. Huang, C. Fang, F. Yang, X. Zeng, and X. Li, "Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits," DAC, 2015.

Digital Library

[18]

C. Fang, Q. Huang, F. Yang, X. Zeng, X. Li, and C. Gu, "Efficient bit error rate estimation for highspeed link by Bayesian model fusion," DATE, pp. 1024--1029, 2015.

Digital Library

[19]

F. Wang, M. Zaheer, X. Li, J. Plouchart and A. Valdes-Garcia, "Co-learning Bayesian model fusion: efficient performance modeling of analog and mixed-signal circuits using side information" ICCAD, pp. 575--582, 2015.

Digital Library

[20]

S. Yu, B. Krishnapuram, R. Rosales and B. Rao, "Bayesian co-training," NIPS, pp. 1--8, 2008.

Digital Library

[21]

C. Bishop, Pattern Recognition and Machine Learning, Springer, 2006.

Digital Library

[22]

J. Tropp and A. Gilbert, "Signal recovery from random measurements via orthogonal matching pursuit," IEEE Trans. Information Theory, vol. 53, no. 12, pp. 4655--4666, Dec. 2007.

Digital Library

[23]

Z. Chen, Y. Wang, J. Driesen and F. Garzia, "Comparison of modeling approaches through hierarchical behavioral modeling of a GNSS receiver front-end," CICC, pp. 1--4, 2013.

[24]

R. Rutenbar, G. Gielen and J. Roychowdhury, "Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs," Proceedings of the IEEE, vol. 95, no. 5, pp. 640--669, Mar. 2007.

[25]

S. Boyd and L. Vandenberghe, Convex Optimization, Cambridge University Press, 2004.

Digital Library

[26]

G. Li, Y. M. Tousi, A. Hassibi and E. Afshari, "Delay-line-based analog-to-digital converters," IEEE TCAS II, vol. 56, no. 6, pp. 464--468, Jun. 2009.

Digital Library

Cited By

Wu NLi YYang HChen HDai SHao CYu CXie Y(2024)Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and ProspectACM Transactions on Design Automation of Electronic Systems10.1145/366130829:4(1-42)Online publication date: 24-Apr-2024
https://dl.acm.org/doi/10.1145/3661308
Fayazi MTaba MAfshari EDreslinski R(2023)AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning ApproachIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.329573770:11(4516-4529)Online publication date: Nov-2023
https://doi.org/10.1109/TCSI.2023.3295737
Zhang XDong DLi CWang SXiao L(2023)A Survey of Machine Learning for Network-on-ChipsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104778(104778)Online publication date: Nov-2023
https://doi.org/10.1016/j.jpdc.2023.104778
Show More Cited By

Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis

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cover image ACM Conferences

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

June 2017

533 pages

ISBN:9781450349277

DOI:10.1145/3061639

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

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Published: 18 June 2017

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DAC '17: The 54th Annual Design Automation Conference 2017

June 18 - 22, 2017

TX, Austin, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Wu NLi YYang HChen HDai SHao CYu CXie Y(2024)Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and ProspectACM Transactions on Design Automation of Electronic Systems10.1145/366130829:4(1-42)Online publication date: 24-Apr-2024
https://dl.acm.org/doi/10.1145/3661308
Fayazi MTaba MAfshari EDreslinski R(2023)AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning ApproachIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.329573770:11(4516-4529)Online publication date: Nov-2023
https://doi.org/10.1109/TCSI.2023.3295737
Zhang XDong DLi CWang SXiao L(2023)A Survey of Machine Learning for Network-on-ChipsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104778(104778)Online publication date: Nov-2023
https://doi.org/10.1016/j.jpdc.2023.104778
Wu NXie Y(2022)A Survey of Machine Learning for Computer Architecture and SystemsACM Computing Surveys10.1145/349452355:3(1-39)Online publication date: 3-Feb-2022
https://dl.acm.org/doi/10.1145/3494523
Wu NXie YHao C(2022)AI-assisted Synthesis in Next Generation EDA: Promises, Challenges, and Prospects2022 IEEE 40th International Conference on Computer Design (ICCD)10.1109/ICCD56317.2022.00039(207-214)Online publication date: Oct-2022
https://doi.org/10.1109/ICCD56317.2022.00039
Fayazi MColter ZAfshari EDreslinski R(2021)Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A ReviewIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2021.306533268:6(2418-2431)Online publication date: Jun-2021
https://doi.org/10.1109/TCSI.2021.3065332
Alawieh MWilliamson SPan D(2019)Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab ModelsProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317896(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317896
Lin YAlawieh MYe WPan D(2018)Machine Learning for Yield Learning and Optimization2018 IEEE International Test Conference (ITC)10.1109/TEST.2018.8624733(1-10)Online publication date: Oct-2018
https://doi.org/10.1109/TEST.2018.8624733

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