Article

Free access

Efficient BIST hardware insertion with low test application time for synthesized data paths

Authors:

Nicola Nicolici,

Bashir M. Al-HashimiAuthors Info & Claims

DATE '99: Proceedings of the conference on Design, automation and test in Europe

Pages 60 - es

https://doi.org/10.1145/307418.307507

Published: 01 January 1999 Publication History

PDF eReader

References

[1]

{1} V.D., Agrawal, C.R., Kime, and K.K. Saluja. A tutorial on built-n self - part 1: Principles. IEEE Design & Test of Computers, pp. 73-92, March 1993.

Digital Library

Google Scholar

[2]

{2} V.D., Agrawal, C.R., Kime, and K.K. Saluja. A tutorial on built-in self test - part 2: Applications. IEEE Design & Test of Computers, pp. 69-77, June 1993.

Digital Library

Google Scholar

[3]

{3} P.R. Chalsani, S. Bhawmik, A. Acharya, and P. Palchaudhuri. Design of testable VLSI circuits with minimum area overhead. In IEEE Transactions on Computers, 38(9), pp. 1460-1462, 1989.

Digital Library

Google Scholar

[4]

{4} A. Basu, T.C. Wilson, D.K. Banerji, and J.C. Majithia. An approach to minimize testability for BILBO based built-in self-test. In Proc. 5th Int. Conf on VLSI Design, pp. 354-355, 1992.

Crossref

Google Scholar

[5]

{5} S.P. Lin, C.A. Njinda, and M.A. Breuer. Generating a family of testable designs using the BILBO methodology. In Journal of Electronic Testing: Theory and Applications (JETTA) 4, pp. 71- 89, April 1993.

Google Scholar

[6]

{6} C.I.H. Chen. Graph partitioning for concurrent test scheduling in VLSI circuits. In Proc. 28th Design Automation Conference, pp. 287-290, 1991.

Digital Library

Google Scholar

[7]

{7} G.L. Craig, C.R. Kime, and K.K. Saluja. Test scheduling and control for VLSI built-in self-test. IEEE Transactions on Computers, 37(9), pp. 1099-1109, 1988.

Digital Library

Google Scholar

[8]

{8} W.B. Jone, C.A. Papachristou, and M. Pereira. A scheme for overlaying concurrent testing of VLSI circuits. In Proc. 26th Design Automation Conference, pp. 531-536, June 1989.

Digital Library

Google Scholar

[9]

{9} A. Orailoglu., and I.G. Harris. Test path generation and test scheduling for self-testable designs. In Proc. International Conference on Computer Design, pp. 528-531, 1993.

Crossref

Google Scholar

[10]

{10} I.G. Harris, and A. Orailoglu. Fine-grained test concurrency in test scheduling for partial-intrusion BIST. In Proc. European Design & Test Conference, pp. 119-123, 1994.

Crossref

Google Scholar

[11]

{11} S. Chiu, and C.A. Papachristou. A design for testability scheme with application to data path synthesis. In Proc. 28th Design Automation Conference, pp. 271-277, June 1991.

Digital Library

Google Scholar

[12]

{12} A.P. Stroele, and H.J. Wunderlich. Hardware-optimal test register insertion. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(6), pp. 531-539, 1998.

Digital Library

Google Scholar

[13]

{13} C.R. Reeves. Modern heuristic techniques for combinatorial problems, McGraw-Hill Book Company, 1995.

Digital Library

Google Scholar

[14]

{14} P. Kollig, and B.M. Al-Hashimi. Simultaneous scheduling, allocation and binding in high level synthesis. IEE Electronics Letters, 33(18), pp. 1516-1518, 1997.

Crossref

Google Scholar

Cited By

View all

Berthelot DFlottes MRouzeyre B(2000)BISTing Data Paths at Behavioral LevelProceedings of the 2000 IEEE International Test Conference10.5555/839295.843665Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843665
Nicolici NAl-Hashimi B(2000)Power Conscious Test Synthesis and Scheduling for BIST RTL Data PathsProceedings of the 2000 IEEE International Test Conference10.5555/839295.843664Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843664
Nicolici NAl-Hashimi B(2000)Power conscious test synthesis and scheduling for BIST RTL data pathsProceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)10.1109/TEST.2000.894261(662-671)Online publication date: 2000
https://doi.org/10.1109/TEST.2000.894261

Index Terms

Efficient BIST hardware insertion with low test application time for synthesized data paths
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization

Recommendations

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

We present an analysis of test application time for test data compression techniques that are used for reducing test data volume and testing time in system-on-a-chip (SOC) designs. These techniques are based on data compression codes and on-chip ...
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume
ITC '02: Proceedings of the 2002 IEEE International Test Conference

Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means of Test Point Insertion (TPI). The state-of-the-art TPI methods only focus ...
Efficient Test Mode Selection & Insertion for RTL-BIST
ITC '00: Proceedings of the 2000 IEEE International Test Conference

Inserting test logic at the Register Transfer Level (RTL),instead of at the gate-level, offers many advantages. Itallows the synthesis process to consider both functionaland test logic together for optimization for meeting thetiming/area/power goals; ...

Comments

Information & Contributors

Information

Published In

DATE '99: Proceedings of the conference on Design, automation and test in Europe

January 1999

730 pages

ISBN:1581131216

DOI:10.1145/307418

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 1999

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DATE99

Sponsor:

SIGDA

DATE99: Design Automation and Test in Europe Conference and Exhibition 1999

Munich, Germany

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
113
Total Downloads

Downloads (Last 12 months)11
Downloads (Last 6 weeks)1

Reflects downloads up to 13 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Berthelot DFlottes MRouzeyre B(2000)BISTing Data Paths at Behavioral LevelProceedings of the 2000 IEEE International Test Conference10.5555/839295.843665Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843665
Nicolici NAl-Hashimi B(2000)Power Conscious Test Synthesis and Scheduling for BIST RTL Data PathsProceedings of the 2000 IEEE International Test Conference10.5555/839295.843664Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843664
Nicolici NAl-Hashimi B(2000)Power conscious test synthesis and scheduling for BIST RTL data pathsProceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)10.1109/TEST.2000.894261(662-671)Online publication date: 2000
https://doi.org/10.1109/TEST.2000.894261

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume

Efficient Test Mode Selection & Insertion for RTL-BIST

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

References

Cited By

Index Terms

Recommendations

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume

Efficient Test Mode Selection & Insertion for RTL-BIST

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Get Access

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations