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Dealing with inductance in high-speed chip design

Authors:

Phillip Restle,

Albert Ruehli,

Steven G. WalkerAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 904 - 909

https://doi.org/10.1145/309847.310096

Published: 01 June 1999 Publication History

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References

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Cited By

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Melikyan VMelikyan V(2018)General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing FactorsSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_1(1-75)Online publication date: 13-Apr-2018
https://doi.org/10.1007/978-3-319-71637-4_1
P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)On-Chip Power Distribution NetworksOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_8(129-144)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_8
Edwards TSteer M(2013)ReferencesFoundations of Interconnect and Microstrip Design10.1002/9781118894514.refs(475-497)Online publication date: 8-Dec-2013
https://doi.org/10.1002/9781118894514.refs
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Index Terms

Dealing with inductance in high-speed chip design
1. Applied computing
  1. Physical sciences and engineering
2. Hardware

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DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1999

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DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

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DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Melikyan VMelikyan V(2018)General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing FactorsSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_1(1-75)Online publication date: 13-Apr-2018
https://doi.org/10.1007/978-3-319-71637-4_1
P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)On-Chip Power Distribution NetworksOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_8(129-144)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_8
Edwards TSteer M(2013)ReferencesFoundations of Interconnect and Microstrip Design10.1002/9781118894514.refs(475-497)Online publication date: 8-Dec-2013
https://doi.org/10.1002/9781118894514.refs
Sharma RChakravarty TBhattacharyya A(2012)Reduction of Signal Overshoots in High-Speed Interconnects Using Adjacent Ground TracksJournal of Electromagnetic Waves and Applications10.1163/15693931079128521824:7(941-950)Online publication date: 3-Apr-2012
https://doi.org/10.1163/156939310791285218
Kozhaya JRestle PQian HPhillips JHu AGraeb H(2011)Myth bustersProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132394(271-275)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132394
Condley WHu XGuthaus MReda SWang J(2010)Analysis of high-performance clock networks with RLC and transmission line effectsProceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction10.1145/1811100.1811113(51-58)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1811100.1811113
Srivastava NQi XBanerjee K(2005)Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated CircuitsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.64(346-351)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.64
Zhong GKoh CRoy KYasuura H(2003)A metric for analyzing effective on-chip inductive couplingProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119803(156-161)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119803
Nourani MAttarha A(2002)Signal IntegrityJournal of Electronic Testing: Theory and Applications10.1023/A:101651412929618:4-5(539-554)Online publication date: 1-Aug-2002
https://dl.acm.org/doi/10.1023/A%3A1016514129296
(2002)Physical Verification and Design Sign-offSystem-on-a-Chip Verification10.1007/0-306-46995-2_8(347-358)Online publication date: 2002
https://doi.org/10.1007/0-306-46995-2_8
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