research-article

Architecture Exploration for HLS-Oriented FPGA Debug Overlays

Authors:

Al-Shahna Jamal,

Jeffrey Goeders,

Steven J.E. WiltonAuthors Info & Claims

FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 209 - 218

https://doi.org/10.1145/3174243.3174254

Published: 15 February 2018 Publication History

Abstract

High-Level Synthesis (HLS) promises improved designer productivity, but requires a debug ecosystem that allows designers to debug in the context of the original source code. Recent work has presented in-system debug frameworks where instrumentation added to the design collects trace data as the circuit runs, and a software tool that allows the user to replay the execution using the captured data. When searching for the root cause of a bug, the designer may need to modify the instrumentation to collect data from a new part of the design, requiring a lengthy recompile.

In this paper, we propose a flexible debug overlay family that provides software-like debug turn-around times for HLS generated circuits. At compile time, the overlay is added to the design and compiled. At debug time, the overlay can be configured many times to implement specific debug scenarios without a recompilation. This paper first outlines a number of "capabilities" that such an overlay should have, and then describes architectural support for each of these capabilities. The cheapest overlay variant allows selective variable tracing with only a 1.7% increase in area overhead from the baseline debug instrumentation, while the deluxe variant offers 2x-7x improvement in trace buffer memory utilization with conditional buffer freeze support.

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Cited By

Wojenski AZbroszczyk HKruszewski MSzymanski PWawrzyn EWielanek DZabolotny WPawlowska DGniazdowski T(2023)Hardware acceleration of complex HEP algorithms with HLS and FPGAs: methodology and preliminary implementationComputer Physics Communications10.1016/j.cpc.2023.108997(108997)Online publication date: Oct-2023
https://doi.org/10.1016/j.cpc.2023.108997
Nafziger ZChua MNoronha DWilton S(2022)Boosting Domain-Specific Debug Through Inter-frame Compression2022 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT56656.2022.9974385(1-10)Online publication date: 5-Dec-2022
https://doi.org/10.1109/ICFPT56656.2022.9974385
Jamal ACahill EGoeders JWilton S(2020)Fast Turnaround HLS Debugging Using Dependency Analysis and Debug OverlaysACM Transactions on Reconfigurable Technology and Systems10.1145/337249013:1(1-26)Online publication date: 28-Jan-2020
https://dl.acm.org/doi/10.1145/3372490
Show More Cited By

Index Terms

Architecture Exploration for HLS-Oriented FPGA Debug Overlays
1. Hardware

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cover image ACM Conferences

FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2018

310 pages

ISBN:9781450356145

DOI:10.1145/3174243

General Chair:
Jason H. Anderson
University of Toronto, Canada
,
Program Chair:
Kia Bazargan
University of Minnesota, USA

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 2018

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FPGA '18

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SIGDA

FPGA '18: The 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 25 - 27, 2018

CALIFORNIA, Monterey, USA

Acceptance Rates

FPGA '18 Paper Acceptance Rate 10 of 116 submissions, 9%;

Overall Acceptance Rate 125 of 627 submissions, 20%

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FPGA '25

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The 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2025

Monterey , CA , USA

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Cited By

Wojenski AZbroszczyk HKruszewski MSzymanski PWawrzyn EWielanek DZabolotny WPawlowska DGniazdowski T(2023)Hardware acceleration of complex HEP algorithms with HLS and FPGAs: methodology and preliminary implementationComputer Physics Communications10.1016/j.cpc.2023.108997(108997)Online publication date: Oct-2023
https://doi.org/10.1016/j.cpc.2023.108997
Nafziger ZChua MNoronha DWilton S(2022)Boosting Domain-Specific Debug Through Inter-frame Compression2022 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT56656.2022.9974385(1-10)Online publication date: 5-Dec-2022
https://doi.org/10.1109/ICFPT56656.2022.9974385
Jamal ACahill EGoeders JWilton S(2020)Fast Turnaround HLS Debugging Using Dependency Analysis and Debug OverlaysACM Transactions on Reconfigurable Technology and Systems10.1145/337249013:1(1-26)Online publication date: 28-Jan-2020
https://dl.acm.org/doi/10.1145/3372490
Holanda Noronha DZhao RGoeders JLuk WWilton SBazargan KNeuendorffer S(2019)On-chip FPGA Debug Instrumentation for Machine Learning ApplicationsProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3289602.3293922(110-115)Online publication date: 20-Feb-2019
https://dl.acm.org/doi/10.1145/3289602.3293922
Ashcraft MGoeders J(2019)Synchronizing On-Chip Software and Hardware Traces for HLS-Accelerated Programs2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00015(54-62)Online publication date: Dec-2019
https://doi.org/10.1109/ICFPT47387.2019.00015
Ashcraft MGoeders J(2018)Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs2018 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2018.00072(354-357)Online publication date: Dec-2018
https://doi.org/10.1109/FPT.2018.00072
Jamal AGoeders JWilton S(2018)An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00076(403-4037)Online publication date: Aug-2018
https://doi.org/10.1109/FPL.2018.00076

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