research-article

Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-based Framework

Authors:

Shahin NazarianAuthors Info & Claims

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

Pages 207 - 212

https://doi.org/10.1145/3194554.3194561

Published: 30 May 2018 Publication History

Abstract

With increasing design complexity, the correlation between test transactions and functional properties becomes non-intuitive, hence impacting the reliability of test generation. This paper presents a modified coverage directed test generation based on an Artificial Neural Network (ANN). The ANN extracts features of test transactions and only those which are learned to be critical, will be sent to the design under verification. Furthermore, the priority of coverage groups is dynamically learned based on the previous test iterations. With ANN-based screening, low-coverage or redundant assertions will be filtered out, which helps accelerate the verification process. This allows our framework to learn from the results of the previous vectors and use that knowledge to select the following test vectors. Our experimental results confirm that our learning-based framework can improve the speed of existing function verification techniques by 24.5x and also also deliver assertion coverage improvement, ranging from 4.3x to 28.9x, compared to traditional coverage directed test generation, implemented in UVM.

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Cited By

Wu NLi YYang HChen HDai SHao CYu CXie Y(2024)Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and ProspectACM Transactions on Design Automation of Electronic Systems10.1145/366130829:4(1-42)Online publication date: 24-Apr-2024
https://dl.acm.org/doi/10.1145/3661308
Saravanan RPudukotai Dinakarrao S(2024)Exploring Coverage Metrics in Hardware Fuzzing: A Comprehensive AnalysisProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3660386(240-245)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3660386
Jin SLi YChen LShi G(2024)SSFuzz:Generating syntactic and semantic seeds for RISC-V processorsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658712(421-426)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658712
Show More Cited By

Index Terms

Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-based Framework
1. Computing methodologies
  1. Machine learning
2. Hardware
  1. Hardware validation
    1. Functional verification

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Published In

cover image ACM Conferences

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

May 2018

533 pages

ISBN:9781450357241

DOI:10.1145/3194554

General Chair:
Deming Chen
University of Illinois, USA
,
Program Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA
IEEE CASS

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 May 2018

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GLSVLSI '18: Great Lakes Symposium on VLSI 2018

May 23 - 25, 2018

IL, Chicago, USA

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GLSVLSI '18 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Wu NLi YYang HChen HDai SHao CYu CXie Y(2024)Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and ProspectACM Transactions on Design Automation of Electronic Systems10.1145/366130829:4(1-42)Online publication date: 24-Apr-2024
https://dl.acm.org/doi/10.1145/3661308
Saravanan RPudukotai Dinakarrao S(2024)Exploring Coverage Metrics in Hardware Fuzzing: A Comprehensive AnalysisProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3660386(240-245)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3660386
Jin SLi YChen LShi G(2024)SSFuzz:Generating syntactic and semantic seeds for RISC-V processorsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658712(421-426)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658712
Ma RYang YLiu ZZhang JLi MHuang JLuo G(2024)VerilogReader: LLM-Aided Hardware Test Generation2024 IEEE LLM Aided Design Workshop (LAD)10.1109/LAD62341.2024.10691801(1-5)Online publication date: 28-Jun-2024
https://doi.org/10.1109/LAD62341.2024.10691801
Xia SZhang YWang ZDing RCui HChen X(2024)An Approach to Enhance the Efficiency of RISC-V Verification Using Intelligent Algorithms2024 IEEE 7th International Conference on Electronic Information and Communication Technology (ICEICT)10.1109/ICEICT61637.2024.10670953(419-423)Online publication date: 31-Jul-2024
https://doi.org/10.1109/ICEICT61637.2024.10670953
Xu JLiu YHe SLin HZhou YWang CCalandrino JTroncoso C(2023)MorFuzzProceedings of the 32nd USENIX Conference on Security Symposium10.5555/3620237.3620311(1307-1324)Online publication date: 9-Aug-2023
https://dl.acm.org/doi/10.5555/3620237.3620311
Bhuvaneswary NDeny JLakshmi A(2023)Hybrid Optimized Verification Methodology using Deep Reinforcement Neural NetworkJournal of Intelligent & Fuzzy Systems: Applications in Engineering and Technology10.3233/JIFS-23213245:3(3715-3728)Online publication date: 1-Jan-2023
https://dl.acm.org/doi/10.3233/JIFS-232132
De SShafique MCorporaal H(2023)Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning ModelsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319797742:4(1133-1146)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3197977
Sohrabizadeh ABai YSun YCong J(2023)Robust GNN-Based Representation Learning for HLS2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323853(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323853
Kandpal J(2023)Machine Learning–Based VLSI Test and VerificationMachine Learning for VLSI Chip Design10.1002/9781119910497.ch3(33-50)Online publication date: 23-Jun-2023
https://doi.org/10.1002/9781119910497.ch3
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